公开(公告)号：US10593690B2

公开(公告)日：2020-03-17

申请号：US16046852

申请日：2018-07-26

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhenyu Lu ,  Simon Shi-Ning Yang ,  Feng Pan ,  Steve Weiyi Yang ,  Jun Chen ,  Guanping Wu ,  Wenguang Shi ,  Weihua Cheng

IPC: H01L27/00 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, multiple through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack, an array interconnection layer in contact with the through array contacts, a peripheral circuit formed on a second substrate. and a peripheral interconnection layer on the peripheral circuit. The array interconnection layer is bonded on the peripheral interconnection layer, such that the peripheral circuit is electrically connected with at least one through array contact.

公开(公告)号：US12137568B2

公开(公告)日：2024-11-05

申请号：US18221358

申请日：2023-07-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhenyu Lu ,  Simon Shi-Ning Yang ,  Feng Pan ,  Steve Weiyi Yang ,  Jun Chen ,  Guanping Wu ,  Wenguang Shi ,  Weihua Cheng

IPC: H10B43/30 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00 ,  H01L25/18 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: A three-dimensional (3D) NAND memory device includes a substrate, a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack to the substrate. The first stack is disposed on the substrate and includes first and second dielectric layers arranged alternately in a vertical direction. The second stack is disposed on the substrate and includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure has an unclosed shape.

公开(公告)号：US11410983B2

公开(公告)日：2022-08-09

申请号：US17115002

申请日：2020-12-08

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Ziqi Chen ,  Chao Li ,  Guanping Wu

IPC: H01L27/11575 ,  H01L25/00 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/00 ,  H01L25/065

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed memory device comprises multiple staircase structures stacked over a substrate. The multiple staircase structures are positioned in a dielectric fill structure over the substrate. Each staircase structure comprises multiple gate electrodes separated by multiple insulating layers. The memory device further comprises a semiconductor channel extending from through the multiple staircase structures into the substrate. A first portion of peripheral via structures extends through the dielectric fill structure and is connected to the gate electrodes of each staircase structure. A second portion of peripheral via structures extend through the dielectric fill structure and is connected to a peripheral device over the substrate and neighboring staircase structures.

公开(公告)号：US20210126005A1

公开(公告)日：2021-04-29

申请号：US17142373

申请日：2021-01-06

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhenyu LU ,  Wenguang Shi ,  Guanping Wu ,  Xianjin Wan ,  Baoyou Chen

IPC: H01L27/11575 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/535

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

公开(公告)号：US10910397B2

公开(公告)日：2021-02-02

申请号：US16727491

申请日：2019-12-26

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhenyu Lu ,  Wenguang Shi ,  Guanping Wu ,  Xianjin Wan ,  Baoyou Chen

IPC: H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/535 ,  H01L27/1157

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

公开(公告)号：US10553604B2

公开(公告)日：2020-02-04

申请号：US16046843

申请日：2018-07-26

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhenyu Lu ,  Wenguang Shi ,  Guanping Wu ,  Xianjin Wan ,  Baoyou Chen

IPC: H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/535 ,  H01L27/1157

Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

公开(公告)号：US11956953B2

公开(公告)日：2024-04-09

申请号：US17934161

申请日：2022-09-21

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhenyu Lu ,  Wenguang Shi ,  Guanping Wu ,  Feng Pan ,  Xianjin Wan ,  Baoyou Chen

IPC: H10B43/00 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/20 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

公开(公告)号：US11728326B2

公开(公告)日：2023-08-15

申请号：US17115143

申请日：2020-12-08

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Ziqi Chen ,  Chao Li ,  Guanping Wu

IPC: H01L27/11575 ,  H01L25/00 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/81895 ,  H01L2224/83896 ,  H01L2924/01014 ,  H01L2924/14511

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the method for forming a memory device includes the following operations. First, a plurality of first semiconductor channels can be formed over a first wafer with a peripheral device and a plurality of first via structures neighboring the plurality of first semiconductor channels. The plurality of first semiconductor channels can extend along a direction perpendicular to a surface of the first wafer. Further, a plurality of second semiconductor channels can be formed over a second wafer with a plurality of second via structures neighboring the plurality of second semiconductor channels. The plurality of second semiconductor channels can extend along a direction perpendicular to a surface of the second wafer and a peripheral via structure.

公开(公告)号：US11482532B2

公开(公告)日：2022-10-25

申请号：US16951141

申请日：2020-11-18

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zhenyu Lu ,  Wenguang Shi ,  Guanping Wu ,  Feng Pan ,  Xianjin Wan ,  Baoyou Chen

IPC: H01L27/00 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565

Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.

公开(公告)号：US10541249B2

公开(公告)日：2020-01-21

申请号：US16126425

申请日：2018-09-10

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Ziqi Chen ,  Guanping Wu

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/535 ,  H01L21/28

Abstract: A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack including multiple first dielectric layers and second dielectric layers on a substrate; forming a channel hole penetrating the alternating dielectric stack, a first diameter of a lower portion of the channel hole being smaller than a second diameter of an upper portion of the channel hole; forming a channel structure including a functional layer in the channel hole, the functional layer including a storage layer; forming an electrode plug in the upper portion of the channel hole; replacing the storage layer in the functional layer in the upper portion of the channel hole with a second insulating layer; and replacing the second dielectric layers in the alternating dielectric stack with conductive layers.