公开(公告)号：US09647671B2

公开(公告)日：2017-05-09

申请号：US14987171

申请日：2016-01-04

Applicant: Wright State University

Inventor： Joseph Strzelecki ,  Saiyu Ren

IPC: H03L7/091 ,  H03K5/135 ,  H03L7/089 ,  H03L7/18 ,  H03K3/356

CPC classification number: H03L7/091 ,  H03K3/356104 ,  H03K5/135 ,  H03L7/0891 ,  H03L7/18

Abstract: A phase frequency detector with two stages of operation; each stage containing two D flip-flops. Each D flip-flop is interconnected to eliminate detection dead zone while avoiding glitches and incorrect output conditions for fast phase locked loop convergence and wide-band applications.

公开(公告)号：US20160218724A1

公开(公告)日：2016-07-28

申请号：US14987171

申请日：2016-01-04

Applicant: Wright State University

Inventor： Joseph Strzelecki ,  Saiyu Ren

IPC: H03L7/091 ,  H03L7/18 ,  H03L7/089 ,  H03K3/037 ,  H03K5/135

CPC classification number: H03L7/091 ,  H03K3/356104 ,  H03K5/135 ,  H03L7/0891 ,  H03L7/18

Abstract: A phase frequency detector with two stages of operation; each stage containing two D flip-flops. Each D flip-flop is interconnected to eliminate detection dead zone while avoiding glitches and incorrect output conditions for fast phase locked loop convergence and wide-band applications.

Abstract translation: 具有两级运行的相位检波器; 每个阶段包含两个D触发器。 每个D触发器互连，以消除检测死区，同时避免毛刺和不正确的输出条件，以实现快速锁相环融合和宽带应用。