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公开(公告)号：US20230069479A1
公开(公告)日：2023-03-02
申请号：US17876499
申请日：2022-07-28
Applicant: Winbond Electronics Corp.
Inventor： Fujimi Kaneko , Makoto Senoo , Takamichi Kasai
Abstract: The disclosure provides a semiconductor storage device and a reading method, which may achieve high-speed processing time for error detection and correction and achieve miniaturization. The flash memory of the disclosure has a NAND chip and an ECC chip. The NAND chip has: a memory array; a page buffer/sensing circuit, including latches L1 and L2 ; and dedicated input and output terminals, which may be used for data transmission with ECC chip. The latch L1 contains cache C0 and cache C1, and the latch L2 only contains the cache C1. The data in the cache C0 of the latch L1 and the data in the cache C1 of the latch L2 are transmitted to the ECC chip. In response to outputting data at the initial address from the ECC chip, the next page is read from the memory array, and the read data is held in the latch L1.
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公开(公告)号：US11488644B2
公开(公告)日：2022-11-01
申请号：US17320224
申请日：2021-05-14
Applicant: Winbond Electronics Corp.
Inventor： Sho Okabe , Makoto Senoo
Abstract: A semiconductor device capable of performing high-speed read or high-reliability read is provided. A reading method of a NAND flash memory includes: pre-charging a sensing node through a voltage-supply node; discharging the sensing node to the voltage-supply node for a prescribed operation; recharging the sensing node by the voltage-supply node after the prescribed operation; and discharging a NAND string and sensing a memory cell.
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公开(公告)号：US20210311826A1
公开(公告)日：2021-10-07
申请号：US17191670
申请日：2021-03-03
Applicant: Winbond Electronics Corp.
Inventor： Makoto Senoo
Abstract: A semiconductor storing apparatus capable of shortening a ECC processing time of a readout operation is provided, including a flash memory includes: a memory cell array; a page buffer/sense circuit holding data read out from a selected page of the memory cell array; an error correcting code circuit receiving data from the page buffer/sense circuit and holding error address information of the data; an output circuit selecting data from the page buffer/sense circuit based on a column address, and outputting the selected data to a data bus; and an error correction part correcting data of the data bus based on the error address information.
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公开(公告)号：US20210035647A1
公开(公告)日：2021-02-04
申请号：US16931406
申请日：2020-07-16
Applicant: Winbond Electronics Corp.
Inventor： Makoto Senoo , Katsutoshi Suito , Tsutomu Taniguchi , Sho Okabe
Abstract: A continuous readout method of a flash memory is provided. Selected bit lines (BL0, BL4, BL8, and BL12) are masked by three non-selected bit lines when data of a cache memory (C0) of a selected page of a memory cell array is read. Selected bit lines (BL2, BL6, BL10, and BL14) are masked by three non-selected bit lines when data of a cache memory (C1) of the same selected page is read. In this way, each of first page data and second page data read from a plurality of selected pages is continuously outputted.
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公开(公告)号：US11735270B2
公开(公告)日：2023-08-22
申请号：US16931406
申请日：2020-07-16
Applicant: Winbond Electronics Corp.
Inventor： Makoto Senoo , Katsutoshi Suito , Tsutomu Taniguchi , Sho Okabe
CPC classification number: G11C16/26 , G11C16/0483
Abstract: A continuous readout method of a flash memory is provided. Selected bit lines (BL0, BL4, BL8, and BL12) are masked by three non-selected bit lines when data of a cache memory (C0) of a selected page of a memory cell array is read. Selected bit lines (BL2, BL6, BL10, and BL14) are masked by three non-selected bit lines when data of a cache memory (C1) of the same selected page is read. In this way, each of first page data and second page data read from a plurality of selected pages is continuously outputted.
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Patent Agency Ranking
公开(公告)号：US20220413748A1
公开(公告)日：2022-12-29
申请号：US17851041
申请日：2022-06-28
Applicant: Winbond Electronics Corp.
Inventor： Makoto Senoo , Katsutoshi Suito
IPC: G06F3/06
Abstract: A semiconductor memory device and an operation method capable of suppressing malfunctions and the like and performing safe operations are provided. A flash memory of the disclosure includes a controller which controls an operation based on a code read from a ROM. The operation method of the disclosure includes detecting whether the code read from the ROM has an error by a CRC processing unit; determining whether to transition to a safe mode when the code having the error is detected; and detecting and correcting the error of the code by an ECC processing unit after transitioning to the safe mode.
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公开(公告)号：US11495297B2
公开(公告)日：2022-11-08
申请号：US17330939
申请日：2021-05-26
Applicant: Winbond Electronics Corp.
Inventor： Makoto Senoo
Abstract: A semiconductor device that can compensate for threshold fluctuations in memory cells using capacitive coupling. The flash memory includes a NAND-type memory cell array, a programing device, a reading device, and an offset voltage determining unit. The programing device programs the memory cells connected to a selected word line. The reading device reads the memory cells connected to a selected word line. The programing device programs the memory cells of a monitoring NAND string simultaneously when programing a word line. The reading device comprises a current detecting unit applying a read voltage to an unselected word line n+1, and detecting the current of the monitoring NAND string. The offset voltage determining unit determines the first and second offset voltage based on the detected current, and a reading pass voltage is applied to the unselected word line, a read voltage is applied to the selected word line.
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公开(公告)号：US10032512B2
公开(公告)日：2018-07-24
申请号：US15641329
申请日：2017-07-05
Applicant: Winbond Electronics Corp.
Inventor： Makoto Senoo , Seow-Fong Lim
IPC: G11C13/00
Abstract: A non-volatile semiconductor memory device includes a memory array 20, including a plurality of memory elements; a selection part, selecting the memory elements of the memory array based on address data; a mode selection part 30, selecting any one of a RAM mode and a flash mode, where the RAM mode is a mode adapted to overwrite data of the memory element according to writing data, and the flash mode is a mode adapted to overwrite data of the memory element when the writing data is a first value and prohibit overwrite when the writing data is a second value; and a write control part, writing the writing data to the selected memory element according to the RAM mode or the flash mode selected by the mode selection part 30.
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公开(公告)号：US20180061496A1
公开(公告)日：2018-03-01
申请号：US15666576
申请日：2017-08-02
Applicant: Winbond Electronics Corp.
Inventor： Makoto Senoo , Naoaki Sudo
CPC classification number: G11C16/16 , G11C7/04 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3459
Abstract: A semiconductor memory device improving a high-temperature data retention is provided. Here, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array. The erasing element further includes an applying element, a verifying element, and a decision element. The applying element applies a monitoring erasing pulse to a monitoring storage cell before starting an erasing operation for selecting the storage cell. The verifying element performs a verification of the monitoring storage cell to which the monitoring erasing pulse is applied. The decision element detennines ISPE conditions based on a verification result of the verifying element. The erasing element erases the storage cell according to the determined ISPE conditions.
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公开(公告)号：US20170365351A1
公开(公告)日：2017-12-21
申请号：US15611791
申请日：2017-06-02
Applicant: Winbond Electronics Corp.
Inventor： Hiroki Murakami , Makoto Senoo
CPC classification number: G11C16/32 , G11C5/066 , G11C7/1066 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/30 , G11C2207/108
Abstract: A voltage generating circuit 100 of the present invention includes a control logic 110, a voltage generating element 120 and a connecting element 130. The voltage generating element 120 includes a plurality of registers A-1, B-1, C-1, D-1, voltage generating blocks A-2, B-2, C-2 and a voltage switch 32. The registers A-1, B-1, C-1, D-1 hold data provided from control logic 110. The voltage generating blocks A-2, B-2, C-2 generate voltage based on voltage control data held by the registers A-1, B-1, C-1. The voltage switch 32 selects voltages based on selection control data held by the register D-1. The connecting element 130 includes signal lines for sequentially transmitting the voltage control data or the selection control data, signal lines for sequentially transmitting a clock signal CLK and signal lines for controlling output of data held by the registers.
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