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公开(公告)号：US20230207020A1
公开(公告)日：2023-06-29
申请号：US17563095
申请日：2021-12-28
Applicant: Winbond Electronics Corp.
Inventor： Koying Huang
Abstract: A memory storage device including a flash memory and a controller circuit is provided. The flash memory includes a plurality of memory cells. Each of the memory cells includes a substrate, a drain terminal, a source terminal, and a gate terminal. The controller circuit is coupled to the flash memory. The controller circuit is configured to perform a first erase operation on the memory cells to obtain a first erase threshold voltage distribution, and perform a program operation on the memory cells to obtain a program threshold voltage distribution. The first erase threshold voltage distribution is larger than a first target voltage. The program threshold voltage distribution is smaller than a second target voltage. The first target voltage is larger than the second target voltage. A writing method of a flash memory is also provided.
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公开(公告)号：US11635913B2
公开(公告)日：2023-04-25
申请号：US15838356
申请日：2017-12-12
Applicant: Winbond Electronics Corp.
Inventor： Koying Huang
Abstract: A NOR flash memory apparatus and a recover and read method for the NOR flash memory apparatus are described. The recover and read method includes: operating a power-up process on the NOR flash memory apparatus during a power-up time period; operating a power-up reading operation and reading a mark bit of a memory block of the flash memory apparatus during a reading time period after the power-up time period; and, applying a negative voltage to a plurality of un-selected word lines for the power-up reading operation to operate without leakage current from bit lines of the memory block being caused and therefore to operate normally without causing mistakes.
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公开(公告)号：US10910051B1
公开(公告)日：2021-02-02
申请号：US16686196
申请日：2019-11-17
Applicant: Winbond Electronics Corp.
Inventor： Koying Huang
Abstract: The disclosure is directed to a method and an apparatus for verifying an operation performed by a cell of a RRAM. In an aspect of the disclosure, the method of verifying an operation performed by a cell of a RRAM would include not limited to performing a first write operation by applying a first write voltage on a cell of the RRAM; measuring a first resistance and a first rate of change of the resistance of the cell; detecting whether the first rate of change of the resistance is below a negative change of resistance threshold; detecting whether the first resistance is below a target resistance value in response to having detected that the first rate of change of the resistance is below the negative change of resistance threshold; and having determined the cell is valid in response to having detected the first resistance dropping below the target resistance value.
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公开(公告)号：US10074436B1
公开(公告)日：2018-09-11
申请号：US15620835
申请日：2017-06-13
Applicant: Winbond Electronics Corp.
Inventor： Koying Huang , Teng Su
CPC classification number: G11C16/32 , G06F11/1048 , G11C7/227 , G11C16/26 , G11C29/24 , G11C29/42 , G11C29/50012
Abstract: A memory device and a data reading method are provided. A dummy circuit performs a read operation in synchronism with a data access circuit according to an address signal, so as to estimate time points at which the data access circuit completes each of operating procedures, and enable the data access circuit to execute a next operating procedure when completing an operating procedure.
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5.发明授权Writing and verifying circuit for a resistive memory and method for writing and verifying a resistive memory 有权用于电阻存储器的写入和验证电路以及用于写入和验证电阻性存储器的方法公开(公告)号：US09312001B1
公开(公告)日：2016-04-12
申请号：US14623507
申请日：2015-02-17
Applicant: Winbond Electronics Corp.
Inventor： Koying Huang
CPC classification number: G11C13/0064 , G11C13/0069 , G11C2013/0066 , G11C2013/009 , G11C2013/0092 , G11C2213/79
Abstract: A writing and verifying circuit and a method for writing and verifying a resistive memory thereof are provided. The steps of the method includes: enabling at least one word line signal corresponding to at least one selected resistive memory cell of the resistive memory during a writing and verifying timing period; providing a bit line voltage to the selected resistive memory cells, wherein the bit line voltage continuously increases or decreases from a first voltage level to a second voltage level during the writing and verifying timing period; and, measuring a detected current through the bit line and determining a finish time point of the writing and verifying timing period according to the detected current and a reference current.
Abstract translation: 提供了写入和验证电路以及用于写入和验证其电阻性存储器的方法。 该方法的步骤包括：在写入和验证定时周期期间使能至少一个字线信号对应于电阻存储器的至少一个选择的电阻性存储单元; 向所选择的电阻存储器单元提供位线电压，其中位线电压在写入和验证定时周期期间从第一电压电平连续地增加或减小到第二电压电平; 并测量通过位线的检测电流，并根据检测到的电流和参考电流确定写入和验证定时周期的完成时间点。
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Patent Agency Ranking
公开(公告)号：US12224021B2
公开(公告)日：2025-02-11
申请号：US18469567
申请日：2023-09-19
Applicant: Winbond Electronics Corp.
Inventor： Koying Huang
Abstract: A memory device includes a controller configured for initiating a program operation for a first column of memory cells which belongs to a group of memory cells; setting a verify condition which comprises a leakage current threshold during a leakage current verifying operation; performing, via a leakage current verifying circuit, a leakage current verifying operation for the first column of the memory cells by applying a negative voltage sweep to each of first remaining M−1 unselected WLs of the M WLs until finding a first negative voltage resulting in the first column of the memory cells having passed leakage current threshold; and applying the program operation for the first column of the memory cells by applying the first negative voltage to each of the first remaining M−1 unselected WLs of the M WLs and a positive bit line voltage for the N BLs.
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公开(公告)号：US12040023B2
公开(公告)日：2024-07-16
申请号：US17563095
申请日：2021-12-28
Applicant: Winbond Electronics Corp.
Inventor： Koying Huang
Abstract: A memory storage device including a flash memory and a controller circuit is provided. The flash memory includes a plurality of memory cells. Each of the memory cells includes a substrate, a drain terminal, a source terminal, and a gate terminal. The controller circuit is coupled to the flash memory. The controller circuit is configured to perform a first erase operation on the memory cells to obtain a first erase threshold voltage distribution, and perform a program operation on the memory cells to obtain a program threshold voltage distribution. The first erase threshold voltage distribution is larger than a first target voltage. The program threshold voltage distribution is smaller than a second target voltage. The first target voltage is larger than the second target voltage. A writing method of a flash memory is also provided.
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公开(公告)号：US11854624B2
公开(公告)日：2023-12-26
申请号：US17530422
申请日：2021-11-18
Applicant: Winbond Electronics Corp.
Inventor： Koying Huang
CPC classification number: G11C16/16 , G11C16/0433 , G11C16/3445 , H10B41/35
Abstract: A non-volatile memory device and a non-volatile memory erasing operation method is provided. The method includes the following. A first erasing operation is performed, including reducing a threshold voltage of each of a plurality of memory cells of the non-volatile memory through a first erasing pulse. A first verification operation is performed to confirm whether the threshold voltage of each of the memory cells is less than an erasing target voltage level. In response to at least one of the memory cells failing the first verification operation, a second erasing operation is performed. The second erasing operation includes selecting the at least one memory cell failing the first verification operation, and reducing the threshold voltage of the at least one memory cell to be less than the erasing target voltage level through a second erasing pulse.
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9.发明授权公开(公告)号：US10790030B1
公开(公告)日：2020-09-29
申请号：US16445224
申请日：2019-06-19
Applicant: Winbond Electronics Corp.
Inventor： Koying Huang
Abstract: A non-volatile memory device and a method thereof that are capable of improving programming speed are introduced. The non-volatile memory device includes a memory array, a charge-pump circuit, a bias detection circuit and a memory controller is introduced. The memory array includes a plurality of memory cells; and a charge-pump circuit is configured to generate a charge-pump voltage. The bias detection circuit is coupled to the charge-pump circuit and is configured to determine whether a level of the charge-pump voltage is less than a first pre-determined threshold value. The memory controller is coupled to the bias detection circuit and is configured to pause a programming operation being performed on at least one of the plurality of memory cells when the bias detection circuit determines that the level of the charge-pump voltage is less than the first pre-determined threshold value.
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10.发明授权公开(公告)号：US10666233B1
公开(公告)日：2020-05-26
申请号：US16275349
申请日：2019-02-14
Applicant: Winbond Electronics Corp.
Inventor： Koying Huang
Abstract: The disclosure is directed to a power drop reset circuit which includes not limited to: a first step circuit configured to detect a change of a power supply voltage per unit of time and transmit an enable signal in response to the first step circuit having determined that the change of the power supply voltage per unit of time has dropped below zero, wherein the first step circuit does not consume any current when the Vcc change per unit of time is greater than or equal to zero; and a second step circuit electrically connected to the first step circuit and configured to detect the Vcc in response to having received the enable signal and generate a power drop reset signal in response to having determined that the Vcc has dropped below a predetermined operating voltage, wherein the second step circuit consumes an operating current after receiving the enable signal.
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