公开(公告)号：US12216804B2

公开(公告)日：2025-02-04

申请号：US18179385

申请日：2023-03-07

Applicant: Wenzhou University

Inventor： Gang Li ,  Hui Li ,  Pengjun Wang ,  Xilong Shao ,  Hao Ye

IPC: H04L9/32 ,  G06F21/75

Abstract: A machine learning attack resistant strong PUF with a dual-edge sampling function comprises switch units, a first arbiter and a second arbiter. The first arbiter is for determining a sequential order of delays at a rising edge of signals input to a first input terminal and a second input terminal of the first arbiter. The second arbiter is for determining a sequential order of delays at a falling edge of signals input to a first input terminal and a second input terminal of the second arbiter. Each switch unit is composed of eight MOS transistors. The strong PUF has a high capacity to resist machine learning attacks and small hardware expenditure through simple structural design of the switch units, realizing machine learning attack resistance and small hardware expenditure at the same time, and generating a large number of challenge response pairs through dual-edge sampling realized by the two arbiters.

公开(公告)号：US10963222B2

公开(公告)日：2021-03-30

申请号：US16418990

申请日：2019-05-21

Applicant: Wenzhou University

Inventor： Pengjun Wang ,  Hongzhen Fang ,  Gang Li ,  Bo Chen

IPC: G06F7/58 ,  H03K3/84

Abstract: A true random number generator with stable node voltage comprises a loop control logic, two inverters identical in structure, two D flip-flops identical in structure, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a monitoring module and a post-processing module. Each inverter comprises a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor and an eleventh PMOS transistor. The true random number generator has the advantages of being able to eliminate the capacitive coupling effect and has high randomness.

公开(公告)号：US11985261B2

公开(公告)日：2024-05-14

申请号：US17900848

申请日：2022-08-31

Applicant: Wenzhou University

Inventor： Pengjun Wang ,  Li Ni ,  Yue Jun Zhang ,  Di Zhou ,  Yijian Shi

IPC: H04L9/32 ,  G06F21/56

CPC classification number: H04L9/3278

Abstract: Disclosed is a software PUF based on an RISC-V processor for IoT security. A 32-bit RISC-V processor is used to generate abnormal information results in an abnormal operating state under a low voltage, and the abnormal information results are used to represent the features of the 32-bit RISC-V processor; 5-bit binary data obtained by comparing the abnormal information results with normal information results has high randomness and uniqueness and it is extremely difficult to directly extract internal abnormal information result from a hardware circuit of the 32-bit RISC-V processor, so modeling attacks based on the 5-bit binary data calculated according to the abnormal information results of the 32-bit RISC-V processor are almost impossible; in addition, when the 32-bit RISC-V processor is in an abnormal operating state, the operating frequency of the 32-bit RISC-V processor is dynamically adjusted through a frequency compensation method.

公开(公告)号：US20220224333A1

公开(公告)日：2022-07-14

申请号：US17541272

申请日：2021-12-03

Applicant: Wenzhou University

Inventor： Pengjun Wang ,  Jiana LIAN ,  Gang Li ,  Ziyu Zhou

IPC: H03K19/003 ,  H03K19/21 ,  H03K3/037 ,  H03K5/01 ,  H03K5/00

Abstract: A strong and weak hybrid PUF circuit comprises N switch units and an arbiter. Each switch unit consists of two delay modules and two 2:1 multiplexers. The N switch units constitute two completely symmetrical delay paths. Each delay module consists of six stages of delay cells. During the operating process, a transmission signal selects a turn-on path of the corresponding 2:1 multiplexers according to activation signals; the switch units in the PUF circuit are in a valid state (if the delay modules are turned on) or in an invalid state (if the delay modules are not turned on) according to whether the delay modules are turned during the operating process; and the strong and weak hybrid PUF circuit can be flexibly configured to be of two different types (a strong PUF circuit and a weak PUF circuit) according to changes of the Hamming weight of input activation signals.

公开(公告)号：US20200167516A1

公开(公告)日：2020-05-28

申请号：US16691622

申请日：2019-11-22

Applicant: Wenzhou University

Inventor： Pengjun Wang ,  Mingbo Wang ,  Bo Chen ,  Gang Li

IPC: G06F30/337

Abstract: A method for integrated optimization of a ternary FPRM circuit comprises: establishing an area estimation model, a power consumption estimation model and a delay estimation model of a ternary FPRM circuit under a p polarity; constructing a correlation between a multi-objective teaching-learning optimization algorithm and optimization of an area, power consumption and a delay of the ternary FPRM circuit; expressing positions of the individuals in the multi-objective teaching-learning optimization algorithm as polarities of the ternary FPRM circuit, and expressing a search space as a space for polarity selection of the ternary FPRM circuit; and finally, searching for a set of Pareto optimum polarity solution for the area, power consumption and delay of the ternary FPRM circuit by means of the multi-objective teaching-learning optimization algorithm to complete the optimization of the area, power consumption and delay for the ternary FPRM circuits.

公开(公告)号：US20190339941A1

公开(公告)日：2019-11-07

申请号：US16404747

申请日：2019-05-07

Applicant: Wenzhou University

Inventor： Pengjun Wang ,  Zhen Li ,  Gang Li ,  Bo Chen

IPC: G06F7/58 ,  G06F9/30

Abstract: A true random number generator with a dynamic compensation capacity comprises a loop control logic, a shift register, a sensitive amplifier and a load matching unit. The sensitive amplifier comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor and two NMOS arrays. Each NMOS array comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor. The load matching unit comprises a first D flip-flop and a second D flip-flop and is configured at an output terminal and an inverted output terminal of the sensitive amplifier. The true random number generator has the advantages of simple feedback regulation and high robustness.

公开(公告)号：US11983885B2

公开(公告)日：2024-05-14

申请号：US17540232

申请日：2021-12-02

Applicant: Wenzhou University

Inventor： Pengjun Wang ,  Songwei Zhao ,  Huiling Chen ,  Suling Xu ,  Wenming He ,  Gang Li

IPC: G06T7/143 ,  G06T7/00

CPC classification number: G06T7/143 ,  G06T7/0012

Abstract: The invention discloses a multi-threshold segmentation method for medical images based on an improved salp swarm algorithm. A two-dimensional histogram is established by means of a grayscale image of a medical image and a non-local mean image, then a salp swarm algorithm is used to determine thresholds selected by a Kapur entropy-based threshold method, and the salp swarm algorithm is improved and mutated by an individual-linked mutation strategy during the threshold selection process to avoid local optimization, so that the segmentation effect on the medical image is optimized; and the method has the advantages of good robustness and high accuracy.

公开(公告)号：US11949409B2

公开(公告)日：2024-04-02

申请号：US18151477

申请日：2023-01-09

Applicant: Wenzhou University

Inventor： Xiangyu Li ,  Pengjun Wang ,  Gang Li

IPC: H03K17/22 ,  G06F1/24

CPC classification number: H03K17/223 ,  G06F1/24

Abstract: A low-power pulse output circuit comprises first to third PMOS transistors, first NMOS to third NMOS transistors, a resistor regulation module, a capacitor regulation module, an inverter and a buffer. Drains of the first PMOS and first NMOS transistors, gates of the first NMOS, second PMOS, second NMOS, and third NMOS transistors are connected. Drain of the second PMOS transistor, gate of the third PMOS transistor and one terminal of the resistor regulation module are connected. The other terminal of the resistor regulation module and drain of the second NMOS transistor are connected. Drain of the third PMOS transistor, drain of the third NMOS transistor and an input terminal of the inverter are connected. An output terminal of the inverter, the other terminal of the capacitor regulation module and an input terminal of the buffer are connected.

公开(公告)号：US11722131B2

公开(公告)日：2023-08-08

申请号：US17801799

申请日：2020-11-23

Applicant: Wenzhou University

Inventor： Pengjun Wang ,  Hai Ming Zhang ,  Yue Jun Zhang ,  Gang Li ,  Bo Chen

IPC: H03K17/00 ,  H03K17/14 ,  G06F1/04 ,  H03K3/037 ,  H03K21/12

CPC classification number: H03K17/145 ,  G06F1/04 ,  H03K3/037 ,  H03K21/12

Abstract: An adaptive anti-aging sensor based on a cuckoo algorithm, comprising a control module, a reference voltage-controlled oscillator, two shaping circuits, a frequency difference circuit, a resolution adjustment circuit, a 16-bit counter, a parallel-to-serial circuit, an adaptive module, and a digital-to-analog converter. A lookup table is prestored in the adaptive module; when aging monitoring is performed on a voltage-controlled oscillator in an integrated circuit, the adaptive module uses the cuckoo algorithm to determines the optimal working voltage of the currently monitored voltage-controlled oscillator, and the control module accordingly changes the input voltage of the voltage-controlled oscillator of the integrated circuit. The present invention has the advantages that the degree of aging of the integrated circuit is reflected by monitoring the degree of aging of the voltage-controlled oscillator in the integrated circuit, and the optimal working voltage of the voltage-controlled oscillator in the integrated circuit is adaptively adjusted.

公开(公告)号：US11632109B2

公开(公告)日：2023-04-18

申请号：US17541272

申请日：2021-12-03

Applicant: Wenzhou University

Inventor： Pengjun Wang ,  Jiana Lian ,  Gang Li ,  Ziyu Zhou

IPC: H03K19/003 ,  H03K19/21 ,  H03K3/037 ,  H03K5/01 ,  H03K5/00

Abstract: A strong and weak hybrid PUF circuit comprises N switch units and an arbiter. Each switch unit consists of two delay modules and two 2:1 multiplexers. The N switch units constitute two completely symmetrical delay paths. Each delay module consists of six stages of delay cells. During the operating process, a transmission signal selects a turn-on path of the corresponding 2:1 multiplexers according to activation signals; the switch units in the PUF circuit are in a valid state (if the delay modules are turned on) or in an invalid state (if the delay modules are not turned on) according to whether the delay modules are turned during the operating process; and the strong and weak hybrid PUF circuit can be flexibly configured to be of two different types (a strong PUF circuit and a weak PUF circuit) according to changes of the Hamming weight of input activation signals.