公开(公告)号：US12216598B2

公开(公告)日：2025-02-04

申请号：US18347642

申请日：2023-07-06

Applicant: WUXI ESIONTECH CO., LTD.

Inventor： Yueer Shan ,  Yanfeng Xu ,  Jicong Fan ,  Tong Liu ,  Hua Yan

IPC: G06F13/20 ,  G06F12/0802

Abstract: An FPGA for implementing data transmission by using a built-in edge module is provided. The FPGA is provided with a built-in edge module. A read port of each resource module connected to the edge module in the FPGA is separately connected to a winding architecture and the edge module, and/or a write port of each resource module connected to the edge module in the FPGA is separately connected to the winding architecture and the edge module. The edge module includes a read/write controller and a cache unit. The read/write controller simultaneously reads data from read ports of a plurality of resource modules and temporarily stores the read data in the cache unit. Alternatively, the read/write controller simultaneously writes temporarily stored data in the cache unit into write ports of the plurality of resource modules.

公开(公告)号：US11604696B2

公开(公告)日：2023-03-14

申请号：US17645314

申请日：2021-12-21

Applicant: WUXI ESIONTECH CO., LTD.

Inventor： Yueer Shan ,  Yanfeng Xu ,  Zhenkai Ji ,  Feng Hui

IPC: G06F11/10 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/16 ,  G06F11/00

Abstract: A field programmable gate array (FPGA) for improving the reliability of a key configuration bitstream by reusing a buffer memory includes a configuration buffer, a configuration memory and a control circuit. The configuration memory includes N configuration blocks. The FPGA stores a key configuration chain by using the configuration buffer and ensures correct content of the key configuration chain through an error correcting code (ECC) check function of the configuration buffer, so that when the FPGA runs normally, a control circuit reads the key configuration chain in the configuration buffer at an interval of a predetermined time and writes the key configuration chain into a corresponding configuration block to update the key configuration chain, thereby ensuring accuracy of the content of the key configuration chain and improving running reliability of the FPGA.

公开(公告)号：US11604692B2

公开(公告)日：2023-03-14

申请号：US17457440

申请日：2021-12-03

Applicant: WUXI ESIONTECH CO., LTD.

Inventor： Yueer Shan ,  Yanfeng Xu ,  Jicong Fan ,  Zhan Jing

IPC: G06F11/10 ,  H03K19/17736 ,  H03K19/1776

Abstract: A field programmable gate array (FPGA) with an automatic error detection and correction function for programmable logic modules includes an error checking and correction device. A check code generation circuit in the error checking and correction device performs error correcting code (ECC) encoding according to input data of corresponding programmable logic registers to generate a check code, and refreshes and writes the check code into a check code register according to a clock signal. A check circuit checks outputs of the programmable logic registers and check code registers to generate syndromes for implementing checking. A decoding circuit generates upset signals corresponding to the syndromes according to a trigger enable pulse of a trigger circuit to control a fault register to directly and asynchronously upset content to correct the error. A circuit area is greatly reduced by using the FPGA, thereby improving a degree of integration of the circuit.

公开(公告)号：US12153809B2

公开(公告)日：2024-11-26

申请号：US17645751

申请日：2021-12-23

Applicant: WUXI ESIONTECH CO., LTD.

Inventor： Yueer Shan ,  Yanfeng Xu ,  Boyin Chen ,  Zhan Jing

IPC: G06F3/06

Abstract: A field-programmable gate array (FPGA) for implementing data transfer between different configuration and application processes includes a programmable logic resource, a configuration memory and a hardware memory. A write port and a read port of the hardware memory are respectively connected to a programmable logic resource by a wiring path, data in the hardware memory remains unchanged at an abnormal running stage of the programmable logic resource, and running data generated by a user design in a configuration and application process can be transferred to a user design in a subsequent configuration and application process by using the hardware memory for use during running. This enlarges functions of the FPGA, and meets application requirements in a plurality of different scenarios.

公开(公告)号：US11736107B2

公开(公告)日：2023-08-22

申请号：US17645456

申请日：2021-12-22

Applicant: WUXI ESIONTECH CO., LTD.

Inventor： Yueer Shan ,  Yanfeng Xu ,  Xiaofei He ,  Jicong Fan

IPC: H03K19/173 ,  H03K3/037

CPC classification number: H03K19/173 ,  H03K3/037

Abstract: A field-programmable gate array (FPGA) for using a configuration shift chain to implement a multi-bitstream function includes a bitstream control circuit, a multi-bitstream configuration shift chain and a configurable module. The FPGA enables multi-bitstream storage configuration bits to latch configuration bitstreams by adjusting a circuit structure of a multi-bitstream configuration shift chain in a combination of a control logic of a bitstream control circuit for the multi-bitstream configuration shift chain, and outputs one latched configuration bitstream from a configuration output terminal to a configurable module through each multi-bitstream storage configuration bit as required, so that the configurable module implements a logic function corresponding to the configuration bitstream outputted by the multi-bitstream configuration shift chain. By switching output of different configuration bitstreams, the FPGA can perform a plurality of times of high-speed switching to implement different logic functions without downloading bitstreams from an off-chip.

公开(公告)号：US12287748B2

公开(公告)日：2025-04-29

申请号：US18446501

申请日：2023-08-09

Applicant: WUXI ESIONTECH CO., LTD.

Inventor： Xiaojie Ma ,  Yanfeng Xu ,  Yuting Xu ,  Boyin Chen ,  Yanfei Zhang ,  Yueer Shan

IPC: G06F13/40 ,  G06F11/27

Abstract: A high-speed low-latency interconnect interface (HLII) for silicon interposer interconnection is provided. The HLII is configured to perform large-scale input/output (I/O) interconnection on a silicon interposer, and includes a physical link (PL) and an LL (LL). The LL receives a data signal, a configuration signal, and a control signal of logical resource inside a chiplet, and can complete data conversion, parity check, training, channel repair, instruction stream generation, and other functions for the PL. The PL receives and transmits a data signal converted by the LL. The PL includes a high-speed I/O port, a first input first output (FIFO), and related control logic. The high-speed I/O port of the PL is compatible with both a double date rate (DDR) transmission mode and a single data rate (SDR) transmission mode.

公开(公告)号：US12229029B2

公开(公告)日：2025-02-18

申请号：US18346892

申请日：2023-07-05

Applicant: WUXI ESIONTECH CO., LTD.

Inventor： Xiaojie Ma ,  Xiaochen Hu ,  Yanfeng Xu ,  Yuting Xu ,  Yanfei Zhang ,  Yueer Shan

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/22 ,  G06F11/27 ,  G06F13/42

Abstract: An apparatus and a method for testing a multi-channel high-speed low-latency interconnect interface (HLII) for a silicon interposer are provided. The apparatus includes: a standard test port configured to exchange a test instruction; an asynchronous bypass port configured to directly access an input/output (I/O) port of a channel of a physical layer of the interconnection interface; a built-in self-test (BIST) engine configured to implement inter-level loopback testing and data verification; a redundant data channel configured to repair a damaged data channel; and a delay chain testing circuit configured to test a function and linearity of a delay chain. The apparatus embeds test and repair logic into the physical layer and a link layer, achieving internal test control without any external controller. In this way, a sample can be tested and quickly screened to ensure its performance.

公开(公告)号：US12009307B2

公开(公告)日：2024-06-11

申请号：US17421460

申请日：2020-12-30

Applicant: WUXI ESIONTECH CO., LTD.

Inventor： Yueer Shan ,  Yanfeng Xu ,  Jicong Fan ,  Yanfei Zhang ,  Hua Yan

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17796

CPC classification number: H01L23/5381 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0652 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17796 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/14211 ,  H01L2924/1424 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/37001

Abstract: The present application discloses a multi-die FPGA implementing a built-in analog circuit using an active silicon connection layer, and relates to the field of FPGA technology. The multi-die FPGA allows multiple small-scale and small-area dies to cascade to achieve large-scale and large-area FPGA products, reducing processing difficulties and improving chip production yields. Meanwhile, due to the existence of the active silicon connection layer, some circuit structures that are difficult to implement within the die and/or occupy a large die area and/or have a low processing requirement can be laid out in the silicon connection layer, solving the existing problems of making these circuit structures directly within the die. Part of the circuit structures can be implemented within the silicon connection layer and the rest in the die, which helps optimize the performance of FPGA products, improve system stability, and reduce system area.

公开(公告)号：US11776915B2

公开(公告)日：2023-10-03

申请号：US17294985

申请日：2020-12-30

Applicant: WUXI ESIONTECH CO., LTD.

Inventor： Jicong Fan ,  Yanfeng Xu ,  Yueer Shan ,  Hua Yan ,  Yanfei Zhang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/535 ,  G06F30/394 ,  G06F30/39 ,  H03K19/17736 ,  G06F15/78 ,  G06F30/347 ,  H10B80/00

CPC classification number: H01L23/5386 ,  G06F15/7825 ,  G06F30/347 ,  G06F30/39 ,  G06F30/394 ,  H01L23/535 ,  H01L24/16 ,  H01L25/0652 ,  H03K19/17736 ,  H03K19/17744 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1431 ,  H01L2924/14361 ,  H10B80/00

Abstract: The present disclosure discloses an FPGA device forming a network-on-chip by using a silicon connection layer. An active silicon connection layer is designed inside the FPGA device. A silicon connection layer interconnection framework is arranged inside the silicon connection layer. Bare die functional modules inside an FPGA bare die are connected to the silicon connection layer interconnection framework to jointly form the network-on-chip. Each bare die functional module and a network interface and a router that are in the silicon connection layer interconnection framework form an NOC node. The NOC nodes intercommunicate with each other, so that the bare die functional modules in the FPGA bare die without a built-in NOC network can achieve efficient intercommunication by means of the silicon connection layer interconnection framework, reducing the processing difficulty on the basis of improving the data transmission bandwidth and performance inside the FPGA device.

公开(公告)号：US11750510B2

公开(公告)日：2023-09-05

申请号：US17236400

申请日：2021-04-21

Applicant: WUXI ESIONTECH CO., LTD.

Inventor： Yanfeng Xu ,  Yueer Shan ,  Jicong Fan ,  Yanfei Zhang ,  Hua Yan

IPC: H04L45/58 ,  H04L49/109

CPC classification number: H04L45/583 ,  H04L49/109

Abstract: The present disclosure discloses an FPGA device for implementing a network-on-chip transmission bandwidth expansion function, and relates to the technical field of FPGAs. When a predefined functional module with built-in hardcore IP nodes is integrated in an FPGA bare die, soft-core IP nodes are configured and formed by using logical resource modules in the FPGA bare die and are connected to the hardcore IP nodes to form an NOC network structure, so as to increase nodes and expand the transmission bandwidth of the predefined functional module. On the other hand, the soft-core IP nodes can be additionally connected to input and output signals in the predefined functional module and also can expand the transmission bandwidth of the predefined functional module.