公开(公告)号：US20100305938A1

公开(公告)日：2010-12-02

申请号：US12855634

申请日：2010-08-12

Applicant: Stewart Sargaison ,  Victor Suba

Inventor： Stewart Sargaison ,  Victor Suba

IPC: G06F9/455

CPC classification number: G06F9/455

Abstract: Emulation systems and method involving invalidating blocks of translated code in emulation of a target system on a host system in are disclosed. One or more blocks of target system code are translated by the host system to produce one or more corresponding blocks of translated code. The host system uses one or more native target system instructions as hints to invalidate or potentially invalidate one or more blocks of translated code. Blocks containing such hints cause the host system to mark some or all of the one or more blocks of translated code as potentially invalid. The potentially invalid blocks may be re-translated immediately. Alternatively, the potentially invalid blocks may be checked to see if the code in these blocks has been modified. If the code has been modified, corresponding blocks of target code may be re-translated.

Abstract translation: 公开了在宿主系统中对目标系统的仿真中使翻译代码块无效化的仿真系统和方法。 目标系统代码的一个或多个块由主机系统翻译以产生一个或多个相应的翻译代码块。 主机系统使用一个或多个本机目标系统指令作为提示使一个或多个翻译代码块无效或潜在地无效。 包含这种提示的块导致主机系统将一个或多个翻译代码块中的一些或全部标记为可能无效。 可能会立即重新翻译潜在的无效块。 或者，可以检查潜在的无效块以查看这些块中的代码是否已被修改。 如果代码已被修改，则可以重新翻译相应的目标代码块。

公开(公告)号：US20070261039A1

公开(公告)日：2007-11-08

申请号：US11696684

申请日：2007-04-04

Applicant: Stewart Sargaison ,  Victor Suba

Inventor： Stewart Sargaison ,  Victor Suba

IPC: G06F9/45

CPC classification number: G06F9/455

Abstract: Emulation systems and method involving invalidating blocks of translated code in emulation of a target system on a host system in are disclosed. One or more blocks of target system code are translated by the host system to produce one or more corresponding blocks of translated code. The host system uses one or more native target system instructions as hints to invalidate or potentially invalidate one or more blocks of translated code. Blocks containing such hints cause the host system to mark some or all of the one or more blocks of translated code as potentially invalid. The potentially invalid blocks may be re-translated immediately. Alternatively, the potentially invalid blocks may be checked to see if the code in these blocks has been modified. If the code has been modified, corresponding blocks of target code may be re-translated.

Abstract translation: 公开了在宿主系统中对目标系统的仿真中使翻译代码块无效化的仿真系统和方法。 目标系统代码的一个或多个块由主机系统翻译以产生一个或多个相应的翻译代码块。 主机系统使用一个或多个本机目标系统指令作为提示使一个或多个翻译代码块无效或潜在地无效。 包含这种提示的块导致主机系统将一个或多个翻译代码块中的一些或全部标记为可能无效。 可能会立即重新翻译潜在的无效块。 或者，可以检查潜在的无效块以查看这些块中的代码是否已被修改。 如果代码已被修改，可能会重新翻译相应的目标代码块。

公开(公告)号：US08219722B2

公开(公告)日：2012-07-10

申请号：US12958138

申请日：2010-12-01

Applicant: Victor Suba ,  Stewart Sargaison ,  Brian Watson

Inventor： Victor Suba ,  Stewart Sargaison ,  Brian Watson

IPC: G06F13/28 ,  G06F15/167 ,  G06F12/00 ,  G06F13/00 ,  G06F9/26 ,  G06F9/34

CPC classification number: G06F9/485 ,  G06F9/45537 ,  G06F9/4881

Abstract: An emulator schedules emulation threads for DMA emulation and other emulation functions in a time-multiplexed manner. Emulation threads are selected for execution according to a load balancing scheme. Non-DMA emulation threads are executed until their execution time period expires or they stall. DMA emulation thread execution is allowed to execute indefinitely until the DMA emulation thread stalls. The DMA emulation thread prefetches additional adjacent data in response to target computer system DMA requests. Upon receiving a target computer system DMA request, the DMA emulation thread first checks to the prefetched data to see if this data matches the request. If so, the request is fulfilled using the prefetched data. If the prefetched data does not match the target computer system DMA request, the DMA emulation thread fetches and stores the requested data and additional adjacent data for potential future use.

Abstract translation: 仿真器以时间复用方式调度DMA仿真和其他仿真功能的仿真线程。 根据负载平衡方案选择仿真线程执行。 执行非DMA仿真线程，直到它们的执行时间段到期或停止。 允许DMA仿真线程执行无限期执行，直到DMA仿真线程停顿。 DMA仿真线程预取附加的相邻数据以响应目标计算机系统DMA请求。 在接收到目标计算机系统DMA请求时，DMA仿真线程首先检查预取的数据以查看该数据是否与请求匹配。 如果是，则使用预取数据来满足请求。 如果预取数据与目标计算机系统DMA请求不匹配，则DMA仿真线程将获取并存储所请求的数据和附加的相邻数据，以备将来使用。

公开(公告)号：US07865702B2

公开(公告)日：2011-01-04

申请号：US12542157

申请日：2009-08-17

Applicant: Victor Suba

Inventor： Victor Suba

IPC: G06F9/48

CPC classification number: G06F8/4441

Abstract: Thread switching prevents pipeline stalls when executing multiple threads. An analysis of a first thread identifies instructions capable of causing pipeline stalls. If pipeline stalls from the identified instructions are likely, thread switching instructions are added to the first thread in place of the identified instructions. Thread switching instructions direct a microprocessor to suspend executing the thread and begin executing a second thread. Thread switching instructions can be added to the second thread to enable the resumption of the first thread at the location specified by the identified instruction. The thread switching instructions are configured to avoid pipeline stalls when switching threads. Thread switching instructions can store and retrieve thread-specific information upon the suspension and resumption of threads. Thread switching instructions can schedule the execution of two or more threads in accordance with load balancing schemes. Threads can be modified using static or dynamic code analysis and modification techniques.

Abstract translation: 执行多个线程时，线程切换可防止流水线停顿。 第一个线程的分析识别能够导致流水线停顿的指令。 如果来自所识别的指令的流水线停顿可能，则线程切换指令被添加到第一线程以代替所识别的指令。 线程切换指令指示微处理器暂停执行线程并开始执行第二个线程。 可以将线程切换指令添加到第二线程，以使得能够在由所识别的指令指定的位置恢复第一线程。 线程切换指令被配置为在切换线程时避免流水线停顿。 线程切换指令可以在线程暂停和恢复时存储和检索线程特定的信息。 线程切换指令可以根据负载平衡方案调度两个或多个线程的执行。 线程可以使用静态或动态代码分析和修改技术进行修改。

公开(公告)号：US20100281292A1

公开(公告)日：2010-11-04

申请号：US12834756

申请日：2010-07-12

Applicant: Stewart Sargaison ,  Victor Suba ,  Brian Watson

Inventor： Stewart Sargaison ,  Victor Suba ,  Brian Watson

IPC: G06F1/04 ,  G06F9/455

CPC classification number: G06F1/12

Abstract: Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is emulated to generate a first set of emulated instructions that emulate a first component on the host system. A second set of code instructions is emulated to generate a second set of emulated instructions that emulate a second component of the target system on the host system. The first set is executed based on a first clock (which may be a fixed clock) and the second set is executed based on a second clock (which may be a variable clock). The host system adjusts the first or second clock, execution of the first or second sets of instructions or a memory access to maintain a desired synchronization between the first and second sets of instructions.

Abstract translation: 公开了用于解决在主机系统上的目标系统仿真中的时钟管理问题的方法和系统。 模拟目标程序的第一组代码指令以产生模拟主机系统上的第一组件的第一组仿真指令。 模拟第二组代码指令以产生模拟主机系统上的目标系统的第二组件的第二组仿真指令。 基于第一时钟（其可以是固定时钟）执行第一集合，并且基于第二时钟（其可以是可变时钟）来执行第二集合。 主机系统调整第一或第二时钟，执行第一组或第二组指令或存储器访问以维持第一组和第二组指令之间的所需同步。

公开(公告)号：US20100305935A1

公开(公告)日：2010-12-02

申请号：US12855656

申请日：2010-08-12

Applicant: Stewart Sargaison ,  Victor Suba

Inventor： Stewart Sargaison ,  Victor Suba

IPC: G06F9/44 ,  G06F9/455

CPC classification number: G06F9/45504

Abstract: Methods and systems for register mapping in emulation of a target system on a host system are disclosed. Statistics for use of a set of registers of a target system processor are determined. Based on the statistics a first subset of the target system registers, including one or more most commonly used registers is determined. The registers in the first subset are directly mapped to a first group of registers of a host system processor. A second subset of the set of target system registers is dynamically mapped to a second group of registers of the host system processor.

Abstract translation: 公开了用于在主机系统上对目标系统进行仿真的寄存器映射的方法和系统。 确定使用目标系统处理器的一组寄存器的统计信息。 基于统计，确定目标系统寄存器的第一子集，包括一个或多个最常用的寄存器。 第一子集中的寄存器被直接映射到主系统处理器的第一组寄存器。 目标系统寄存器集合的第二个子集被动态地映射到主机系统处理器的第二组寄存器。

公开(公告)号：US07792666B2

公开(公告)日：2010-09-07

申请号：US11696684

申请日：2007-04-04

Applicant: Stewart Sargaison ,  Victor Suba

Inventor： Stewart Sargaison ,  Victor Suba

IPC: G06F9/455

CPC classification number: G06F9/455

Abstract: Emulation systems and method involving invalidating blocks of translated code in emulation of a target system on a host system in are disclosed. One or more blocks of target system code are translated by the host system to produce one or more corresponding blocks of translated code. The host system uses one or more native target system instructions as hints to invalidate or potentially invalidate one or more blocks of translated code. Blocks containing such hints cause the host system to mark some or all of the one or more blocks of translated code as potentially invalid. The potentially invalid blocks may be re-translated immediately. Alternatively, the potentially invalid blocks may be checked to see if the code in these blocks has been modified. If the code has been modified, corresponding blocks of target code may be re-translated.

Abstract translation: 公开了在宿主系统中对目标系统的仿真中使翻译代码块无效化的仿真系统和方法。 目标系统代码的一个或多个块由主机系统翻译以产生一个或多个相应的翻译代码块。 主机系统使用一个或多个本机目标系统指令作为提示使一个或多个翻译代码块无效或潜在地无效。 包含这种提示的块导致主机系统将一个或多个翻译代码块中的一些或全部标记为可能无效。 可能会立即重新翻译潜在的无效块。 或者，可以检查潜在的无效块以查看这些块中的代码是否已被修改。 如果代码已被修改，则可以重新翻译相应的目标代码块。

公开(公告)号：US20100017582A1

公开(公告)日：2010-01-21

申请号：US12542157

申请日：2009-08-17

Applicant: Victor Suba

Inventor： Victor Suba

IPC: G06F9/30

CPC classification number: G06F8/4441

Abstract: Thread switching prevents pipeline stalls when executing multiple threads. An analysis of a first thread identifies instructions capable of causing pipeline stalls. If pipeline stalls from the identified instructions are likely, thread switching instructions are added to the first thread in place of the identified instructions. Thread switching instructions direct a microprocessor to suspend executing the thread and begin executing a second thread. Thread switching instructions can be added to the second thread to enable the resumption of the first thread at the location specified by the identified instruction. The thread switching instructions are configured to avoid pipeline stalls when switching threads. Thread switching instructions can store and retrieve thread-specific information upon the suspension and resumption of threads. Thread switching instructions can schedule the execution of two or more threads in accordance with load balancing schemes. Threads can be modified using static or dynamic code analysis and modification techniques.

Abstract translation: 执行多个线程时，线程切换可防止流水线停顿。 第一个线程的分析识别能够导致流水线停顿的指令。 如果来自所识别的指令的流水线停顿可能，则线程切换指令被添加到第一线程以代替所识别的指令。 线程切换指令指示微处理器暂停执行线程并开始执行第二个线程。 可以将线程切换指令添加到第二线程，以使得能够在由所识别的指令指定的位置恢复第一线程。 线程切换指令被配置为在切换线程时避免流水线停顿。 线程切换指令可以在线程暂停和恢复时存储和检索线程特定的信息。 线程切换指令可以根据负载平衡方案调度两个或多个线程的执行。 线程可以使用静态或动态代码分析和修改技术进行修改。

公开(公告)号：US07568189B2

公开(公告)日：2009-07-28

申请号：US11740636

申请日：2007-04-26

Applicant: Victor Suba ,  Stewart Saragaison ,  Brian Watson

Inventor： Victor Suba ,  Stewart Saragaison ,  Brian Watson

IPC: G06F9/45

CPC classification number: G06F8/51 ,  G06F9/45516

Abstract: An emulator uses code translation and recompilation to execute target computer system applications on a host computer system. Target application code is partitioned into target application code blocks, and related target application code blocks are combined into block groups and translated. Translated application code block groups are sized to comply with restrictions on branch instruction size. Upon selecting an application code block group for execution, a cache tag is used to determine if a corresponding translated code block group is available and valid. If not, the block group is translated and executed. Sequentially executed translated code blocks are located in adjacent portions of memory to improve performance when switching between translated code blocks. The emulator may use a link register of the host computer system to prefetch instructions and data from translated code blocks. The emulator also takes into account structural hazards in translating instructions.

Abstract translation: 仿真器使用代码转换和重新编译来在主机系统上执行目标计算机系统应用程序。 目标应用程序代码被划分为目标应用程序代码块，并将相关目标应用程序代码块组合成块组并进行转换。 翻译的应用程序代码块组的大小应符合分支指令大小的限制。 在选择用于执行的应用代码块组时，使用高速缓存标签来确定相应的转换的代码块组是否可用且有效。 如果没有，则块组被翻译并执行。 顺序执行的转换代码块位于存储器的相邻部分，以在转换的代码块之间切换时提高性能。 仿真器可以使用主计算机系统的链接寄存器来从转换的代码块预取指令和数据。 仿真器还考虑到翻译指令中的结构危害。

公开(公告)号：US08392171B2

公开(公告)日：2013-03-05

申请号：US12855656

申请日：2010-08-12

Applicant: Stewart Sargaison ,  Victor Suba

Inventor： Stewart Sargaison ,  Victor Suba

IPC: G06F9/44 ,  G06F9/455 ,  G06F15/00

CPC classification number: G06F9/45504

Abstract: Methods and systems for register mapping in emulation of a target system on a host system are disclosed. Statistics for use of a set of registers of a target system processor are determined. Based on the statistics a first subset of the target system registers, including one or more most commonly used registers is determined. The registers in the first subset are directly mapped to a first group of registers of a host system processor. A second subset of the set of target system registers is dynamically mapped to a second group of registers of the host system processor.

Abstract translation: 公开了用于在主机系统上对目标系统进行仿真的寄存器映射的方法和系统。 确定使用目标系统处理器的一组寄存器的统计信息。 基于统计，确定目标系统寄存器的第一子集，包括一个或多个最常用的寄存器。 第一子集中的寄存器被直接映射到主机系统处理器的第一组寄存器。 目标系统寄存器集合的第二个子集被动态地映射到主机系统处理器的第二组寄存器。