公开(公告)号：US20170032975A1

公开(公告)日：2017-02-02

申请号：US14811852

申请日：2015-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Chi Tai ,  Chun-Ju Tao ,  Chung-Che Huang

IPC: H01L21/3213 ,  H01L21/311 ,  H01L29/45 ,  H01L29/49 ,  H01L21/283 ,  H01L21/768 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/32136 ,  H01L21/02063 ,  H01L21/28176 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76814 ,  H01L21/76897 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor process for treating a metal gate includes the following steps. A metal gate including a main conductive material on a substrate is provided. A H2/N2 plasma treatment process is performed to reduce the main conductive material.

Abstract translation: 用于处理金属栅极的半导体工艺包括以下步骤。 提供了在基板上包括主导电材料的金属栅极。 执行H2 / N2等离子体处理工艺以减少主导电材料。

公开(公告)号：US20150179748A1

公开(公告)日：2015-06-25

申请号：US14138153

申请日：2013-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Kun-I Chou ,  Chung-Che Huang ,  Chia-Cheng Hsu ,  Mu-Jia Liu

IPC: H01L29/423 ,  H01L29/66

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成图案化的多层电介质膜; 在图案化的多层电介质膜上形成图案化的叠层，使得图案化的多层电介质膜的边缘从图案化的叠层露出; 形成覆盖层以覆盖基板的一部分并暴露图案化的叠层和图案化多层电介质膜的暴露边缘; 通过使用覆盖层和图案化叠层作为蚀刻掩模去除图案化的多层电介质膜的暴露边缘的至少一部分; 以及通过使用覆盖层作为蚀刻掩模进行离子注入工艺以形成掺杂区域。

公开(公告)号：US09040423B2

公开(公告)日：2015-05-26

申请号：US13943900

申请日：2013-07-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wan-Fang Chung ,  Ping-Chia Shih ,  Hsiang-Chen Lee ,  Che-Hao Chang ,  Jhih-Long Lin ,  Wei-Pin Huang ,  Shao-Nung Huang ,  Yu-Cheng Wang ,  Jaw-Jiun Tu ,  Chung-Che Huang

IPC: H01L21/311 ,  H01L21/306

CPC classification number: H01L21/306 ,  H01L21/30604 ,  H01L21/31105 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/66825

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.

Abstract translation: 提供一种制造半导体器件的方法。 提供了具有第一区域和第二多晶硅层的基板，第一区域具有第一多晶硅层和第二区域。 然后在第二区域中的第一区域中的第一多晶硅层的第一多晶硅层之上沉积氮化物HM膜，并在第二区域中的第二多晶硅层上方沉积氮化物HM膜。 之后，在第一区域中的氮化物HM膜上形成第一图案化钝化物以覆盖氮化物HM膜和第一器件，并且在第二区域中的第二多晶硅层之上形成第二图案化钝化。 第二区域中的第二多晶硅层由第二图案化钝化限定。

公开(公告)号：US09613826B2

公开(公告)日：2017-04-04

申请号：US14811852

申请日：2015-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Chi Tai ,  Chun-Ju Tao ,  Chung-Che Huang

IPC: H01L21/283 ,  H01L21/3213 ,  H01L29/51 ,  H01L21/311 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L29/45

CPC classification number: H01L21/32136 ,  H01L21/02063 ,  H01L21/28176 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76814 ,  H01L21/76897 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor process for treating a metal gate includes the following steps. A metal gate including a main conductive material on a substrate is provided. A H2/N2 plasma treatment process is performed to reduce the main conductive material.

公开(公告)号：US09412851B2

公开(公告)日：2016-08-09

申请号：US14138153

申请日：2013-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Kun-I Chou ,  Chung-Che Huang ,  Chia-Cheng Hsu ,  Mu-Jia Liu

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L27/11573

Abstract: A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成图案化的多层电介质膜; 在图案化的多层电介质膜上形成图案化的叠层，使得图案化的多层电介质膜的边缘从图案化的叠层露出; 形成覆盖层以覆盖基板的一部分并暴露图案化的叠层和图案化多层电介质膜的暴露边缘; 通过使用覆盖层和图案化叠层作为蚀刻掩模去除图案化的多层电介质膜的暴露边缘的至少一部分; 以及通过使用覆盖层作为蚀刻掩模进行离子注入工艺以形成掺杂区域。

公开(公告)号：US20150024598A1

公开(公告)日：2015-01-22

申请号：US13943900

申请日：2013-07-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wan-Fang Chung ,  Ping-Chia Shih ,  Hsiang-Chen Lee ,  Che-Hao Chang ,  Jhih-Long Lin ,  Wei-Pin Huang ,  Shao-Nung Huang ,  Yu-Cheng Wang ,  Jaw-Jiun Tu ,  Chung-Che Huang

IPC: H01L21/306

CPC classification number: H01L21/306 ,  H01L21/30604 ,  H01L21/31105 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/66825

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.

Abstract translation: 提供一种制造半导体器件的方法。 提供了具有第一区域和第二多晶硅层的基板，第一区域具有第一多晶硅层和第二区域。 然后在第二区域中的第一区域中的第一多晶硅层的第一多晶硅层之上沉积氮化物HM膜，并在第二区域中的第二多晶硅层上方沉积氮化物HM膜。 之后，在第一区域中的氮化物HM膜上形成第一图案化钝化物以覆盖氮化物HM膜和第一器件，并且在第二区域中的第二多晶硅层之上形成第二图案化钝化。 第二区域中的第二多晶硅层由第二图案化钝化限定。