公开(公告)号：US11139374B2

公开(公告)日：2021-10-05

申请号：US16536412

申请日：2019-08-09

Applicant: The Hong Kong University of Science And Technology

Inventor： Jing Chen ,  Qingkai Qian

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/08

Abstract: Field-effect transistors (FETs) are described that comprise a semiconducting gate (SG) layer, referred to herein as SG-FETs. In one or more embodiments, the FETs can include a channel layer and a SG layer capacitively coupled to the channel layer. The SG layer has an embedded voltage-clamping function that provides internal gate over voltage protection without an additional protection circuit. The embedded voltage-clamping function is based on the SG layer having a maximum effective gate voltage that is clamped to the depletion threshold of the SG layer.

公开(公告)号：US20200052071A1

公开(公告)日：2020-02-13

申请号：US16536412

申请日：2019-08-09

Applicant: The Hong Kong University of Science And Technology

Inventor： Jing Chen ,  Qingkai Qian

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/423

Abstract: Field-effect transistors (FETs) are described that comprise a semiconducting gate (SG) layer, referred to herein as SG-FETs. In one or more embodiments, the FETs can include a channel layer and a SG layer capacitively coupled to the channel layer. The SG layer has an embedded voltage-clamping function that provides internal gate over voltage protection without an additional protection circuit. The embedded voltage-clamping function is based on the SG layer having a maximum effective gate voltage that is clamped to the depletion threshold of the SG layer.

公开(公告)号：US09337028B2

公开(公告)日：2016-05-10

申请号：US14585636

申请日：2014-12-30

Applicant: The Hong Kong University of Science and Technology

Inventor： Jing Chen ,  Sen Huang ,  Qimeng Jiang ,  Zhikai Tang

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L21/0254 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: Passivation of group III-nitride hetero junction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.

Abstract translation: 本文描述了III族氮化物异质结器件的钝化。 钝化有助于同时实现有效/高电流塌陷抑制和低泄漏电流，而不需要使用复杂的多场板技术。 可以通过等离子体增强的原子层沉积在III族氮化物基异质结装置的表面上生长电荷极化AlN薄膜来实现钝化，使得在界面处诱导正极化电荷以补偿大部分负极 在界面收费。

公开(公告)号：US11705511B2

公开(公告)日：2023-07-18

申请号：US16325711

申请日：2017-08-16

Applicant: The Hong Kong University of Science and Technology

Inventor： Jing Chen ,  Mengyuan Hua

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/66462

Abstract: Structures, devices and methods are provided for forming an interface protection layer (204) adjacent to a fully or partially recessed gate structure (202) of a group III nitride, a metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) device or a metal-insulator-semiconductor field-effect transistor (MIS-FET) device, and forming agate dielectric (114) disposed the interface protection layer (204).

公开(公告)号：US08937336B2

公开(公告)日：2015-01-20

申请号：US13895511

申请日：2013-05-16

Applicant: The Hong Kong University of Science and Technology

Inventor： Jing Chen ,  Sen Huang ,  Qimeng Jiang ,  Zhikai Tang

IPC: H01L31/102 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L21/0254 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: Passivation of group III-nitride heterojunction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.

Abstract translation: 本文描述了III族氮化物异质结装置的钝化。 钝化有助于同时实现有效/高电流塌陷抑制和低泄漏电流，而不需要使用复杂的多场板技术。 可以通过等离子体增强的原子层沉积在III族氮化物基异质结装置的表面上生长电荷极化AlN薄膜来实现钝化，使得在界面处诱导正极化电荷以补偿大部分负极 在界面收费。

公开(公告)号：US09160326B2

公开(公告)日：2015-10-13

申请号：US13936386

申请日：2013-07-08

Applicant: The Hong Kong University of Science and Technology

Inventor： Jing Chen ,  Man Ho Kwan

IPC: H03K17/081 ,  H01L27/095 ,  H01L21/8252 ,  H01L27/06

CPC classification number: H03K17/08104 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/095

Abstract: Providing gate protection to a group III-semiconductor device by delivering gate overdrive immunity is described herein. The gate protection can be achieved by embedding a gate-voltage-controlling second transistor to the gate electrode of a first transistor. In other words, a first gate electrode of the first semiconductor device is in series with a second source electrode of the second semiconductor device, and a second gate electrode of the second semiconductor device is connected to the second source electrode and the first gate electrode.

Abstract translation: 本文描述了通过提供栅极过驱动免疫来为III组半导体器件提供栅极保护。 栅极保护可以通过将栅极电压控制的第二晶体管嵌入到第一晶体管的栅电极来实现。 换句话说，第一半导体器件的第一栅电极与第二半导体器件的第二源电极串联，并且第二半导体器件的第二栅电极连接到第二源电极和第一栅电极。

公开(公告)号：US10404251B2

公开(公告)日：2019-09-03

申请号：US16097808

申请日：2017-05-03

Applicant: The Hong Kong University of Science and Technology

Inventor： Jing Chen ,  Gaofei Tang

IPC: H03K17/687 ,  H03K17/0412 ,  H02M1/08 ,  H03K17/06

Abstract: The technology described herein is generally directed towards a self-bootstrap integrated gate driver circuit with high driving speed, enhanced driving capability and rail-to-rail output. A capacitor and diode are used with a first inverter coupled to a control signal input terminal, a second inverter coupled to the first inverter, a push-pull circuit comprising a pull-up transistor and a pull-down transistor and a power device comprising a power device transistor with a gate. Control signal input at one state controls the first inverter to a first output state, turns on the pull-down transistor to discharge the gate of the power device transistor, turns off the power device and charges the capacitor through the diode. The control signal input in another state controls the first inverter to a second output state, turns off the pull-down transistor and turns on the pull-up transistor via the capacitor to turn on the power device.

公开(公告)号：US10270436B2

公开(公告)日：2019-04-23

申请号：US15526744

申请日：2015-11-13

Applicant: The Hong Kong University of Science and Technology

Inventor： Jing Chen ,  Baikui Li ,  Xi Tang

IPC: H01L27/15 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L33/00 ,  H01L33/32 ,  H01L33/36 ,  H03K17/06 ,  H01L29/205 ,  H01L29/207 ,  H01L29/417 ,  H01L29/778

Abstract: Techniques are provided that pumping of deep traps in GaN electronic devices using photons from an on-chip photon source. In various embodiments, a method for optical pumping of deep traps in GaN HEMTs is provided using an on-chip integrated photon source that is configured to generate photons during operation of the HEMT. In an aspect, the on-chip photon source is a SoH-LED. In various additional embodiments, an integration scheme is provided that integrates the photon source into the drain electrode of a HEMT, thereby converting the conventional HEMT with an ohmic drain to a transistor with hybrid photonic-ohmic drain (POD), a POD transistor or PODFET for short.