公开(公告)号：US09812358B1

公开(公告)日：2017-11-07

申请号：US15264718

申请日：2016-09-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chun Huang ,  Ting-Ting Chen ,  Yu-Chung Su ,  Ling-Fu Nieh ,  Pin-Chuan Su ,  Teng-Chun Tsai ,  Tai-Chun Huang ,  Joy Cheng

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/28123 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/66795 ,  H01L29/7851

Abstract: FinFET structures and methods of forming the same are disclosed. In a method, a recess is formed exposing a plurality of semiconductor fins on a wafer. A dummy contact material is formed in the recess. The dummy contact material contains carbon. The dummy contact material is cured with one or more baking steps. The one or more baking steps harden the dummy contact material. A first portion of the dummy contact material is replaced with an inter-layer dielectric. A second portion of the dummy contact material is replaced with a plurality of contacts. The plurality of contacts are electrically coupled to source/drain regions of the plurality of semiconductor fins.

公开(公告)号：US20160099331A1

公开(公告)日：2016-04-07

申请号：US14968652

申请日：2015-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Clement Hsingjen Wann ,  Sey-Ping Sun ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Li-Chi Yu ,  Chun Hsiung Tsai ,  Chin-Hsiang Lin ,  Neng-Kuo Chen ,  Meng-Chun Chang ,  Ta-Chun Ma ,  Gin-Chen Huang ,  Yen-Chun Huang

IPC: H01L29/45 ,  H01L29/161 ,  H01L29/417 ,  H01L27/088

CPC classification number: H01L21/28518 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

Abstract translation: 提供具有外延区域和双金属 - 半导体合金表面的器件。 外延区域包括面向上的小面和面向下的小面。 面向上的小面具有第一金属 - 半导体合金表面，并且朝下小面具有第二金属 - 半导体合金表面，其中第一金属 - 半导体合金不同于第二金属 - 半导体合金。

公开(公告)号：US09281193B2

公开(公告)日：2016-03-08

申请号：US14729262

申请日：2015-06-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chun Huang ,  Chih-Ming Lai ,  Ken-Hsien Hsieh ,  Ming-Feng Shieh

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/32 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a first pattern having a first feature of a first material on a semiconductor substrate. A second pattern with a second feature and third feature of a second material, interposed by the first feature, is formed on the semiconductor substrate. Spacer elements then are formed on sidewalls of the first feature, the second feature, and the third feature. After forming the spacer elements, the second material comprising the second and third features is selectively removed to form a first opening and a second opening. The first feature, the first opening and the second opening are used as a masking element to etch the target layer.

Abstract translation: 一种方法包括在半导体衬底上形成具有第一材料的第一特征的第一图案。 具有由第一特征插入的第二材料的第二特征和第三特征的第二图案形成在半导体衬底上。 间隔元件然后形成在第一特征，第二特征和第三特征的侧壁上。 在形成间隔元件之后，选择性地移除包括第二和第三特征的第二材料以形成第一开口和第二开口。 第一特征，第一开口和第二开口用作掩模元件以蚀刻目标层。

公开(公告)号：US10354923B2

公开(公告)日：2019-07-16

申请号：US15610266

申请日：2017-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chun Huang ,  Bang-Tai Tang ,  Chih-Tang Peng ,  Tai-Chun Huang

IPC: H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L21/31 ,  H01L21/469

Abstract: A method includes performing an atomic layer deposition (ALD) process to deposit a dielectric material over a substrate, curing the deposited dielectric material using an ultra violet (UV) light, and annealing the deposited dielectric material after the curing.

公开(公告)号：US20180090491A1

公开(公告)日：2018-03-29

申请号：US15280703

申请日：2016-09-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chun Huang ,  Chih-Tang Peng ,  Kuang-Yuan Hsu ,  Tai-Chun Huang ,  Tsu-Hsiu Perng ,  Tien-I Bao

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/306 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311

Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.

公开(公告)号：US09437712B2

公开(公告)日：2016-09-06

申请号：US14201391

申请日：2014-03-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chun Huang ,  Bor Chiuan Hsieh ,  Tai-Chun Huang ,  Chia-Ying Lee ,  Tze-Liang Lee

IPC: H01L23/48 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/31116 ,  H01L21/76829 ,  H01L21/76897

Abstract: A method embodiment includes forming a protective liner over the substrate and forming an inter-layer dielectric over the protective liner. The protective liner covers a sidewall of a gate spacer. The method further includes patterning a contact opening in the first ILD to expose a portion of the protective liner. The portion of the protective liner in the contact opening is removed to expose an active region at a top surface of the semiconductor substrate. A contact is formed in the contact opening. The contact is electrically connected to the active region.

Abstract translation: 方法实施例包括在衬底上形成保护性衬垫并在保护性衬垫上形成层间电介质。 保护衬套覆盖栅极间隔件的侧壁。 该方法还包括图案化第一ILD中的接触开口以暴露保护性衬垫的一部分。 去除接触开口中的保护衬垫的部分以露出半导体衬底的顶表面处的有源区。 在接触开口中形成接触。 触点电连接到有源区。

公开(公告)号：US20150255275A1

公开(公告)日：2015-09-10

申请号：US14201391

申请日：2014-03-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yen-Chun Huang ,  Bor Chiuan Hsieh ,  Tai-Chun Huang ,  Chia-Ying Lee ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/31116 ,  H01L21/76829 ,  H01L21/76897

Abstract: A method embodiment includes forming a protective liner over the substrate and forming an inter-layer dielectric over the protective liner. The protective liner covers a sidewall of a gate spacer. The method further includes patterning a contact opening in the first ILD to expose a portion of the protective liner. The portion of the protective liner in the contact opening is removed to expose an active region at a top surface of the semiconductor substrate. A contact is formed in the contact opening. The contact is electrically connected to the active region.

Abstract translation: 方法实施例包括在衬底上形成保护性衬垫并在保护性衬垫上形成层间电介质。 保护衬套覆盖栅极间隔件的侧壁。 该方法还包括图案化第一ILD中的接触开口以暴露保护性衬垫的一部分。 去除接触开口中的保护衬垫的部分以露出半导体衬底的顶表面处的有源区。 在接触开口中形成接触。 触点电连接到有源区。

公开(公告)号：US11222826B2

公开(公告)日：2022-01-11

申请号：US16685758

申请日：2019-11-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chun Huang ,  Chih-Tang Peng ,  Kuang-Yuan Hsu ,  Tai-Chun Huang ,  Tsu-Hsiu Perng ,  Tien-I Bao

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088

Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.

公开(公告)号：US10483169B2

公开(公告)日：2019-11-19

申请号：US15280703

申请日：2016-09-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chun Huang ,  Chih-Tang Peng ,  Kuang-Yuan Hsu ,  Tai-Chun Huang ,  Tsu-Hsiu Perng ,  Tien-I Bao

IPC: H01L21/8234 ,  H01L21/762

Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.

公开(公告)号：US20180350693A1

公开(公告)日：2018-12-06

申请号：US15610266

申请日：2017-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chun Huang ,  Bang-Tai Tang ,  Chih-Tang Peng ,  Tai-Chun Huang

IPC: H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02348 ,  H01L21/823431 ,  H01L27/088

Abstract: A method includes performing an atomic layer deposition (ALD) process to deposit a dielectric material over a substrate, curing the deposited dielectric material using an ultra violet (UV) light, and annealing the deposited dielectric material after the curing.