公开(公告)号：US11271104B2

公开(公告)日：2022-03-08

申请号：US16578293

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Ting Lu ,  Pei-Lun Wang ,  Yu-Chang Jong

IPC: H01L29/40 ,  H01L29/78 ,  H01L23/495 ,  H01L29/66 ,  H01L21/761 ,  H01L29/417 ,  H01L23/485 ,  H01L29/10 ,  H01L29/06

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a gate structure over a substrate and between a source region and a drain region. A composite etch stop structure is formed over the gate structure and a first inter-level dielectric (ILD) layer is formed over the composite etch stop structure. The composite etch stop structure has a plurality of stacked dielectric materials. The first ILD layer is etched to concurrently define contact openings extending to the substrate and a field plate opening extending to the composite etch stop structure. The contact openings and the field plate opening are concurrently filled with one or more conductive materials.

公开(公告)号：US20200373395A1

公开(公告)日：2020-11-26

申请号：US16417735

申请日：2019-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Hui-Ting Lu ,  Pei-Lun Wang ,  Yu-Chang Jong ,  Jyun-Guan Jhou

IPC: H01L29/40 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/765 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate disposed over a drift region. A first gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an outer sidewall of the first gate electrode to the drain region. The etch stop layer overlies the drift region disposed between the source region and the drain region. A field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate overlies the drift region. A top surface of the field plate is aligned with a top surface of the first gate electrode and a bottom surface of the field plate is vertically above a bottom surface of the first gate electrode. The field plate and first gate electrode respectively include metal materials.

公开(公告)号：US20170148911A1

公开(公告)日：2017-05-25

申请号：US15424333

申请日：2017-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Liang Chou ,  Dah-Chuen Ho ,  Hui-Ting Lu ,  Po-Chih Su ,  Pei-Lun Wang ,  Yu-Chang Jong

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L23/49562 ,  H01L23/49575 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7835

Abstract: The present disclosure relates to a transistor device having a field plate, and a method of formation. In some embodiments, the transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers laterally extend from over the gate electrode to a location between the gate electrode and the drain region. A field plate is located within an inter-level dielectric (ILD) layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the location and vertically extends from the one or more dielectric layers to a top surface of the ILD layer. A conductive contact is arranged over the drain region and is surrounded by the ILD layer. The conductive contact extends to the top surface of the ILD layer.

公开(公告)号：US11335784B2

公开(公告)日：2022-05-17

申请号：US16952438

申请日：2020-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Hui-Ting Lu ,  Pei-Lun Wang ,  Yu-Chang Jong ,  Jyun-Guan Jhou

IPC: H01L29/40 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/765 ,  H01L21/8238

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a source region and a drain region within a substrate. A drift region is formed within the substrate such that the drift region is disposed laterally between the source region and the drain region. A first gate structure is formed over the drift region. An inter-level dielectric (ILD) layer is formed over the first gate structure. The ILD layers is patterned to define a field plate opening. A first field plate layer, a second field plate layer, and a third field plate layer are formed within the field plate opening.

公开(公告)号：US09954097B2

公开(公告)日：2018-04-24

申请号：US15424333

申请日：2017-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Liang Chou ,  Dah-Chuen Ho ,  Hui-Ting Lu ,  Po-Chih Su ,  Pei-Lun Wang ,  Yu-Chang Jong

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L23/49562 ,  H01L23/49575 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7835

Abstract: The present disclosure relates to a transistor device having a field plate, and a method of formation. In some embodiments, the transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers laterally extend from over the gate electrode to a location between the gate electrode and the drain region. A field plate is located within an inter-level dielectric (ILD) layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the location and vertically extends from the one or more dielectric layers to a top surface of the ILD layer. A conductive contact is arranged over the drain region and is surrounded by the ILD layer. The conductive contact extends to the top surface of the ILD layer.

公开(公告)号：US20160149007A1

公开(公告)日：2016-05-26

申请号：US14604885

申请日：2015-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Liang Chou ,  Dah-Chuen Ho ,  Hui-Ting Lu ,  Po-Chih Su ,  Pei-Lun Wang ,  Yu-Chang Jong

IPC: H01L29/40 ,  H01L29/10 ,  H01L21/321 ,  H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/45

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L23/49562 ,  H01L23/49575 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7835

Abstract: The present disclosure relates to a high voltage transistor device having a field plate, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to a drift region arranged between the gate electrode and the drain region. A field plate is located within a first inter-level dielectric layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the drift region and vertically extends from the dielectric layer to a top surface of the first ILD layer. A plurality of metal contacts, having a same material as the field plate, vertically extend from a bottom surface of the first ILD layer to a top surface of the first ILD layer.

Abstract translation: 本公开涉及一种具有场板的高压晶体管器件及其形成方法。 在一些实施例中，高压晶体管器件具有设置在位于衬底内的源极区域和漏极区域之间的衬底上的栅电极。 电介质层从栅极电极上方横向延伸到布置在栅极电极和漏极区域之间的漂移区域。 场板位于覆盖衬底的第一级间介电层内。 场板从栅电极上方横向延伸到漂移区上方，并从电介质层垂直延伸到第一ILD层的顶表面。 具有与场板相同的材料的多个金属触点从第一ILD层的底表面垂直延伸到第一ILD层的顶表面。

公开(公告)号：US20200020803A1

公开(公告)日：2020-01-16

申请号：US16578293

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Ting Lu ,  Pei-Lun Wang ,  Yu-Chang Jong

IPC: H01L29/78 ,  H01L29/40 ,  H01L23/495 ,  H01L29/66 ,  H01L21/761 ,  H01L29/417

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a gate structure over a substrate and between a source region and a drain region. A composite etch stop structure is formed over the gate structure and a first inter-level dielectric (ILD) layer is formed over the composite etch stop structure. The composite etch stop structure has a plurality of stacked dielectric materials. The first ILD layer is etched to concurrently define contact openings extending to the substrate and a field plate opening extending to the composite etch stop structure. The contact openings and the field plate opening are concurrently filled with one or more conductive materials.

公开(公告)号：US20180219093A1

公开(公告)日：2018-08-02

申请号：US15927281

申请日：2018-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Liang Chou ,  Dah-Chuen Ho ,  Hui-Ting Lu ,  Po-Chih Su ,  Pei-Lun Wang ,  Yu-Chang Jong

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L23/49562 ,  H01L23/49575 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7835

Abstract: The present disclosure, in some embodiments, relates to a transistor device having a field plate. The transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers are arranged over the gate electrode, and a field plate is arranged over the one or more dielectric layers. The field plate extends from a first outermost sidewall that is directly over an upper surface of the gate electrode to a second outermost sidewall that is between the gate electrode and the drain region and that extends to below the upper surface of the gate electrode.

公开(公告)号：US10964810B2

公开(公告)日：2021-03-30

申请号：US16578292

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsueh-Liang Chou ,  Dah-Chuen Ho ,  Hui-Ting Lu ,  Po-Chih Su ,  Pei-Lun Wang ,  Yu-Chang Jong

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/761 ,  H01L23/495 ,  H01L29/10

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.

公开(公告)号：US10756208B2

公开(公告)日：2020-08-25

申请号：US16174626

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Ting Lu ,  Pei-Lun Wang ,  Yu-Chang Jong

IPC: H01L29/78 ,  H01L29/40 ,  H01L23/495 ,  H01L29/66 ,  H01L21/761 ,  H01L29/417 ,  H01L23/485 ,  H01L29/10 ,  H01L29/06

Abstract: The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a gate structure disposed over a substrate between source and drain regions and a dielectric layer laterally extending from over the gate structure to between the gate structure and the drain region. A composite etch stop layer having a plurality of different dielectric materials is stacked over the dielectric layer. A contact etch stop layer directly contacts an upper surface and sidewalls of the composite etch stop layer. A field plate is laterally surrounded by a first inter-level dielectric (ILD) layer and vertically extends from a top of the first ILD layer, through the contact etch stop layer, and into the composite etch stop layer.