公开(公告)号：US12293910B2

公开(公告)日：2025-05-06

申请号：US18359552

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chuan Wang ,  Guan-Xuan Chen ,  Chia-Yang Hung ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

公开(公告)号：US20240387517A1

公开(公告)日：2024-11-21

申请号：US18786525

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chuan Wang ,  Guan-Xuan Chen ,  Chia-Yang Hung ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L27/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a gate electrode, a gate electrode contact layer over the gate electrode, forming a dielectric layer over the gate electrode contact layer, and performing an etch through the dielectric layer, the etch forming an opening that exposes the gate electrode contact layer. The method further includes performing a post-etch treatment on the opening formed by the etch process by exposing the opening to a plasma. The method further includes forming gate electrode contacts in the openings after the post-etch treatment by a bottom-up deposition process.

公开(公告)号：US20240363408A1

公开(公告)日：2024-10-31

申请号：US18766863

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Chih Hsiung ,  Jyun-De Wu ,  Peng Wang ,  Huan-Just Lin

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/535 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76895 ,  H01L21/02252 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76829 ,  H01L23/535 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first etch stop layer from a portion of a gate mask, the gate mask extending between spacers adjacent a gate electrode, the gate electrode overlying a semiconductor fin. The method further includes forming a second etch stop layer adjacent the first etch stop layer, forming an opening through the second etch stop layer, and exposing the first etch stop layer by performing a first etching process. The method further includes extending the opening through the first etch stop layer and exposing the gate electrode by performing a second etching process. Once the gate electrode has been exposed, the method further includes forming a gate contact in the opening.

公开(公告)号：US12040233B2

公开(公告)日：2024-07-16

申请号：US17329998

申请日：2021-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng Jhe Tsai ,  Hong-Jie Yang ,  Meng-Chun Chang ,  Hao Chiang ,  Chia-Ying Lee ,  Huan-Just Lin ,  Chuan Chang

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

公开(公告)号：US20230343648A1

公开(公告)日：2023-10-26

申请号：US18345148

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Jyun Wu ,  Hung-Chi Wu ,  Chia-Ching Lee ,  Pin-Hsuan Yeh ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/0234 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

公开(公告)号：US20230282484A1

公开(公告)日：2023-09-07

申请号：US18316307

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Jyun Wu ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/28 ,  H01L21/8238 ,  G03F7/09 ,  H01L29/66 ,  H01L21/027 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01L21/32 ,  H01L21/30 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L21/28185 ,  H01L21/823842 ,  G03F7/091 ,  H01L21/823814 ,  H01L29/66545 ,  H01L21/0276 ,  H01L21/28088 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/4966 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01L21/823821 ,  H01L21/28176 ,  H01L21/28158 ,  H01L21/32 ,  H01L21/30 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/28211 ,  H01L21/02252 ,  H01L21/0234

Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

公开(公告)号：US20220262792A1

公开(公告)日：2022-08-18

申请号：US17339452

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yang-Cheng Wu ,  Yun-Hua Chen ,  Wen-Kuo Hsieh ,  Huan-Just Lin

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/306

Abstract: In an embodiment, a method includes: depositing a protective layer on a source/drain region and a gate mask, the gate mask disposed on a gate structure, the gate structure disposed on a channel region of a substrate, the channel region adjoining the source/drain region; etching an opening through the protective layer, the opening exposing the source/drain region; depositing a metal in the opening and on the protective layer; annealing the metal to form a metal-semiconductor alloy region on the source/drain region; and removing residue of the metal from the opening with a cleaning process, the protective layer covering the gate mask during the cleaning process.

公开(公告)号：US11227788B2

公开(公告)日：2022-01-18

申请号：US16921015

申请日：2020-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Teng-Chun Tsai ,  Bing-Hung Chen ,  Chien-Hsun Wang ,  Cheng-Tung Lin ,  Chih-Tang Peng ,  De-Fang Chen ,  Huan-Just Lin ,  Li-Ting Wang ,  Yung-Cheng Lu

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/311 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/41

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

公开(公告)号：US20210358811A1

公开(公告)日：2021-11-18

申请号：US17391220

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Jyun Wu ,  Hung-Chi Wu ,  Chia-Ching Lee ,  Pin-Hsuan Yeh ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

公开(公告)号：US11081396B2

公开(公告)日：2021-08-03

申请号：US16568518

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Jyun Wu ,  Hung-Chi Wu ,  Chia-Ching Lee ,  Pin-Hsuan Yeh ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.