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公开(公告)号：US20150014846A1
公开(公告)日：2015-01-15
申请号：US13940626
申请日：2013-07-12
Applicant: Taiwan Semiconductor Manufacturing Co., LTD.
Inventor： Yu-Chia Lai , Hsien-Ming Tu , Tung-Liang Shao , Hsien-Wei Chen , Chang-Pin Huang , Ching-Jung Yang
IPC: H01L23/00
CPC classification number: H01L24/11 , H01L21/563 , H01L23/3192 , H01L24/02 , H01L24/05 , H01L24/13 , H01L2224/02235 , H01L2224/0225 , H01L2224/02255 , H01L2224/02313 , H01L2224/0233 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/05548 , H01L2224/10125 , H01L2224/11015 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2924/01029 , H01L2924/181 , H01L2924/01082 , H01L2924/01047 , H01L2924/00012 , H01L2924/014 , H01L2924/00
Abstract: A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.
Abstract translation: 封装半导体器件包括半导体衬底，金属焊盘，金属基底，聚合物绝缘层，含铜结构和导电凸块。 金属焊盘和金属基底设置在半导体衬底上。 聚合物绝缘层覆盖金属基底和半导体基底。 含铜结构设置在聚合物绝缘层之上，并且包括支撑结构和钝化后互连（PPI）线。 支撑结构与金属基座对准。 PPI线部分地位于支撑结构内，并且通过支撑结构的开口延伸出，其中支撑结构的顶部升高到高于PPI线的顶部。 导电凸块由支撑结构保持。
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公开(公告)号：US10062654B2
公开(公告)日：2018-08-28
申请号：US15214463
申请日：2016-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Chia Lai , Chen-Hua Yu , Chang-Pin Huang , Chung-Shi Liu , Hsien-Ming Tu , Hung-Yi Kuo , Hao-Yi Tsai , Shih-Wei Liang , Ren-Xuan Liu
IPC: H01L23/52 , H01L23/58 , H01L23/522 , H01L23/31 , H01L23/00
CPC classification number: H01L23/585 , H01L23/3185 , H01L23/5226 , H01L24/05 , H01L24/17 , H01L2224/0237 , H01L2924/01013 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074
Abstract: A semiconductor structure has an integrated circuit component, a conductive contact pad, a seal ring structure, a conductive via, a ring barrier, and a mold material. The conductive contact pad is disposed on and electrically connected with the integrated circuit component. The seal ring structure is disposed on the integrated circuit component and surrounding the conductive contact pad. The conductive via is disposed on and electrically connected with the conductive contact pad. The ring barrier is disposed on the seal ring structure. The ring barrier surrounds the conductive via. The mold material covers side surfaces of the integrated circuit component. A semiconductor manufacturing process is also provided.
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公开(公告)号：US09048149B2
公开(公告)日：2015-06-02
申请号：US13940626
申请日：2013-07-12
Applicant: Taiwan Semiconductor Manufacturing Co., LTD.
Inventor： Yu-Chia Lai , Hsien-Ming Tu , Tung-Liang Shao , Hsien-Wei Chen , Chang-Pin Huang , Ching-Jung Yang
IPC: H01L23/00
CPC classification number: H01L24/11 , H01L21/563 , H01L23/3192 , H01L24/02 , H01L24/05 , H01L24/13 , H01L2224/02235 , H01L2224/0225 , H01L2224/02255 , H01L2224/02313 , H01L2224/0233 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/05548 , H01L2224/10125 , H01L2224/11015 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2924/01029 , H01L2924/181 , H01L2924/01082 , H01L2924/01047 , H01L2924/00012 , H01L2924/014 , H01L2924/00
Abstract: A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.
Abstract translation: 封装半导体器件包括半导体衬底，金属焊盘，金属基底，聚合物绝缘层，含铜结构和导电凸块。 金属焊盘和金属基底设置在半导体衬底上。 聚合物绝缘层覆盖金属基底和半导体基底。 含铜结构设置在聚合物绝缘层之上，并且包括支撑结构和钝化后互连（PPI）线。 支撑结构与金属基座对准。 PPI线部分地位于支撑结构内，并且通过支撑结构的开口延伸出，其中支撑结构的顶部升高到高于PPI线的顶部。 导电凸块由支撑结构保持。
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Patent Agency Ranking
公开(公告)号：US09852985B1
公开(公告)日：2017-12-26
申请号：US15275460
申请日：2016-09-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Chia Lai , Chen-Hua Yu , Chang-Pin Huang , Chung-Shi Liu , Hsien-Ming Tu , Hung-Yi Kuo , Hao-Yi Tsai , Shih-Wei Liang , Ren-Xuan Liu
IPC: H01L23/52 , H01L23/528 , H01L23/522 , H01L23/31 , H01L23/00
CPC classification number: H01L23/528 , H01L23/3171 , H01L23/5226 , H01L24/05 , H01L24/06 , H01L2224/05624 , H01L2224/05647
Abstract: A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The conductive pad is disposed on and electrically to the integrated circuit. The dielectric layer covers the integrated circuit and the conductive pad, the dielectric layer includes a plurality of contact openings arranged in array, and the conductive pad is partially exposed by the contact openings. The conductive via is disposed on the dielectric layer and electrically connected to the conductive pad through the contact openings. The conductive via includes a plurality of convex portions arranged in array. The convex portions are distributed on a top surface of the conductive via, and the convex portions are corresponding to the contact openings.
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公开(公告)号：US20170372999A1
公开(公告)日：2017-12-28
申请号：US15275460
申请日：2016-09-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Chia Lai , Chen-Hua Yu , Chang-Pin Huang , Chung-Shi Liu , Hsien-Ming Tu , Hung-Yi Kuo , Hao-Yi Tsai , Shih-Wei Liang , Ren-Xuan Liu
IPC: H01L23/528 , H01L23/522 , H01L23/31 , H01L23/00
CPC classification number: H01L23/528 , H01L23/3171 , H01L23/5226 , H01L24/05 , H01L24/06 , H01L2224/05624 , H01L2224/05647
Abstract: A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The conductive pad is disposed on and electrically to the integrated circuit. The dielectric layer covers the integrated circuit and the conductive pad, the dielectric layer includes a plurality of contact openings arranged in array, and the conductive pad is partially exposed by the contact openings. The conductive via is disposed on the dielectric layer and electrically connected to the conductive pad through the contact openings. The conductive via includes a plurality of convex portions arranged in array. The convex portions are distributed on a top surface of the conductive via, and the convex portions are corresponding to the contact openings.
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6.发明授权公开(公告)号：US09799615B1
公开(公告)日：2017-10-24
申请号：US15214466
申请日：2016-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chang-Pin Huang , Chung-Shi Liu , Hsien-Ming Tu , Hung-Yi Kuo , Hao-Yi Tsai , Shih-Wei Liang , Yu-Chia Lai , Ren-Xuan Liu
CPC classification number: H01L21/566 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/585 , H01L24/19 , H01L24/20 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2924/18162 , H01L2924/35121 , H01L2924/37001
Abstract: Package structures and methods of forming the same are disclosed. A package structure includes a die, a molding member and a redistribution circuit structure. The die includes a semiconductor substrate, a connector and a passivation layer. The semiconductor substrate has a top surface. The connector is disposed over the top surface of the semiconductor substrate. The passivation layer is disposed over the top surface of the semiconductor substrate and exposes a portion of the connector. The molding member laterally surrounds the semiconductor substrate, wherein a top surface of the molding member is higher than the top surface of the semiconductor substrate and the molding member forms a hooking structure that embraces over an edge portion of the semiconductor substrate. The redistribution circuit structure extends over the passivation layer and the molding member, and is electrically connected to the connector.
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公开(公告)号：US20180025997A1
公开(公告)日：2018-01-25
申请号：US15214463
申请日：2016-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Chia Lai , Chen-Hua Yu , Chang-Pin Huang , Chung-Shi Liu , Hsien-Ming Tu , Hung-Yi Kuo , Hao-Yi Tsai , Shih-Wei Liang , Ren-Xuan Liu
IPC: H01L23/58 , H01L23/31 , H01L23/00 , H01L23/522
CPC classification number: H01L23/585 , H01L23/3185 , H01L23/5226 , H01L24/05 , H01L24/17 , H01L2224/0237 , H01L2924/01013 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074
Abstract: A semiconductor structure has an integrated circuit component, a conductive contact pad, a seal ring structure, a conductive via, a ring barrier, and a mold material. The conductive contact pad is disposed on and electrically connected with the integrated circuit component. The seal ring structure is disposed on the integrated circuit component and surrounding the conductive contact pad. The conductive via is disposed on and electrically connected with the conductive contact pad. The ring barrier is disposed on the seal ring structure. The ring barrier surrounds the conductive via. The mold material covers side surfaces of the integrated circuit component. A semiconductor manufacturing process is also provided.
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公开(公告)号：US09318456B2
公开(公告)日：2016-04-19
申请号：US14694780
申请日：2015-04-23
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yu-Chia Lai , Hsien-Ming Tu , Tung-Liang Shao , Hsien-Wei Chen , Chang-Pin Huang , Ching-Jung Yang
CPC classification number: H01L24/11 , H01L21/563 , H01L23/3192 , H01L24/02 , H01L24/05 , H01L24/13 , H01L2224/02235 , H01L2224/0225 , H01L2224/02255 , H01L2224/02313 , H01L2224/0233 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/05548 , H01L2224/10125 , H01L2224/11015 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2924/01029 , H01L2924/181 , H01L2924/01082 , H01L2924/01047 , H01L2924/00012 , H01L2924/014 , H01L2924/00
Abstract: A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.
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