公开(公告)号：US20180268881A1

公开(公告)日：2018-09-20

申请号：US15702881

申请日：2017-09-13

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akio SUGAHARA ,  Yoshikazu Harada ,  Shoichiro Hashimoto

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G11C5/025 ,  G11C7/222

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US10991402B2

公开(公告)日：2021-04-27

申请号：US16838091

申请日：2020-04-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akio Sugahara ,  Yoshikazu Harada ,  Shoichiro Hashimoto

IPC: G11C5/02 ,  G11C7/10 ,  G11C7/22

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US20190206453A1

公开(公告)日：2019-07-04

申请号：US16298525

申请日：2019-03-11

Applicant: Toshiba Memory Corporation

Inventor： Akio Sugahara ,  Yoshikazu Harada ,  Shoichiro Hashimoto

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G11C5/025 ,  G11C7/222

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US10650869B2

公开(公告)日：2020-05-12

申请号：US16298525

申请日：2019-03-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akio Sugahara ,  Yoshikazu Harada ,  Shoichiro Hashimoto

IPC: G11C5/02 ,  G11C7/10 ,  G11C7/22

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

公开(公告)号：US10276221B2

公开(公告)日：2019-04-30

申请号：US15702881

申请日：2017-09-13

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akio Sugahara ,  Yoshikazu Harada ,  Shoichiro Hashimoto

IPC: G11C7/10

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.