公开(公告)号：US09647676B2

公开(公告)日：2017-05-09

申请号：US15206433

申请日：2016-07-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu Nandan Srinivasa ,  Tharun Nagulu

IPC: H03M1/06 ,  H03M1/12 ,  G06F1/32 ,  G06F13/40 ,  H03M1/38 ,  H03M1/00 ,  H03M1/80 ,  H03M1/46

CPC classification number: H03M1/124 ,  G06F1/3287 ,  G06F13/4022 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1245 ,  H03M1/38 ,  H03M1/466 ,  H03M1/468 ,  H03M1/804

Abstract: The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an array of MSB (most significant bit) capacitors, an array of LSB (least significant bit) capacitors, and an error correction capacitor. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A successive approximation register (SAR) state machine is coupled to the zero crossing detector and operates the charge sharing DAC in a sampling mode and a conversion mode. During the sampling mode an input voltage is provided to the array of MSB capacitors and the error correction capacitor.

公开(公告)号：US20160336952A1

公开(公告)日：2016-11-17

申请号：US15206433

申请日：2016-07-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raghu Nandan Srinivasa ,  Tharun Nagulu

IPC: H03M1/12 ,  G06F1/32 ,  G06F13/40 ,  H03M1/38 ,  H03M1/46

CPC classification number: H03M1/124 ,  G06F1/3287 ,  G06F13/4022 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1245 ,  H03M1/38 ,  H03M1/466 ,  H03M1/468 ,  H03M1/804

Abstract: The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an array of MSB (most significant bit) capacitors, an array of LSB (least significant bit) capacitors, and an error correction capacitor. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A successive approximation register (SAR) state machine is coupled to the zero crossing detector and operates the charge sharing DAC in a sampling mode and a conversion mode. During the sampling mode an input voltage is provided to the array of MSB capacitors and the error correction capacitor.

Abstract translation: 本公开提供了逐次逼近寄存器模数转换器（SAR ADC）。 SAR ADC包括一个电荷共享DAC，包括一个MSB（最高有效位）电容阵列，一个LSB​​（最低有效位）电容器阵列和一个纠错电容器。 零交叉检测器耦合到电荷共享DAC。 过零检测器产生数字输出。 逐次逼近寄存器（SAR）状态机耦合到过零检测器，并以采样模式和转换模式操作电荷共享DAC。 在采样模式期间，向MSB电容器阵列和纠错电容器提供输入电压。

公开(公告)号：US09391627B1

公开(公告)日：2016-07-12

申请号：US14871475

申请日：2015-09-30

Applicant: Texas Instruments Incorporated

Inventor： Raghu Nandan Srinivasa ,  Tharun Nagulu

IPC: H03M1/06 ,  H03M1/00 ,  H03M1/46 ,  H03M1/12 ,  H03M1/80

CPC classification number: H03M1/124 ,  G06F1/3287 ,  G06F13/4022 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1245 ,  H03M1/38 ,  H03M1/466 ,  H03M1/468 ,  H03M1/804

Abstract: The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an array of MSB (most significant bit) capacitors, an array of LSB (least significant bit) capacitors, and an error correction capacitor. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A successive approximation register (SAR) state machine is coupled to the zero crossing detector and operates the charge sharing DAC in a sampling mode and a conversion mode. During the sampling mode an input voltage is provided to the array of MSB capacitors and the error correction capacitor.

Abstract translation: 本公开提供了逐次逼近寄存器模数转换器（SAR ADC）。 SAR ADC包括一个电荷共享DAC，包括一个MSB（最高有效位）电容阵列，一个LSB​​（最低有效位）电容器阵列和一个纠错电容器。 零交叉检测器耦合到电荷共享DAC。 过零检测器产生数字输出。 逐次逼近寄存器（SAR）状态机耦合到过零检测器，并以采样模式和转换模式操作电荷共享DAC。 在采样模式期间，向MSB电容器阵列和纠错电容器提供输入电压。