公开(公告)号：US11527486B2

公开(公告)日：2022-12-13

申请号：US17121077

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chen-Hua Yu ,  Wei-Ting Chen ,  Chieh-Yen Chen

IPC: H01L23/498 ,  H01K3/10 ,  H05K1/16 ,  H05K1/18 ,  H01L23/552 ,  H01L25/00 ,  H01L25/07 ,  H01L25/16

Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

公开(公告)号：US11239157B2

公开(公告)日：2022-02-01

申请号：US16995779

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Wei-Ting Chen

IPC: H01L23/522 ,  H01L23/00 ,  H01L49/02 ,  H01L21/768 ,  H01L23/532 ,  H01L21/56

Abstract: A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.

公开(公告)号：US20210305226A1

公开(公告)日：2021-09-30

申请号：US16830282

申请日：2020-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Wei-Ting Chen

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L23/29 ,  H01L23/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/538 ,  H01L21/683 ,  H01L25/065

Abstract: Embodiments of the disclosure provide a package structure and method of forming the same. The package structure includes a first die, a first encapsulant, a first RDL structure, a die stack structure and a second encapsulant. The first encapsulant laterally encapsulates the first die. The first RDL structure is electrically connected to the first die, and disposed on a first side of the first die and the first encapsulant. The die stack structure is electrically connected to the first die and disposed on a second side of the first die opposite to the first side. The second encapsulant is located over the first encapsulant and laterally encapsulating the die stack structure. A sidewall of the first encapsulant is aligned with a sidewall of the second encapsulant.

公开(公告)号：US11062998B2

公开(公告)日：2021-07-13

申请号：US16547567

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Wei-Ting Chen ,  Chien-Hsun Chen ,  Shih-Ya Huang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

Abstract: A semiconductor package includes dies, a redistribution structure, a conductive structure and connectors. The conductive plate is electrically connected to contact pads of at least two dies and is disposed on redistribution structure. The conductive structure includes a conductive plate and a solder cover, and the conductive structure extend over the at least two dies. The connectors are disposed on the redistribution structure, and at least one connector includes a conductive pillar. The conductive plate is at same level height as conductive pillar. The vertical projection of the conductive plate falls on spans of the at least two dies.

公开(公告)号：US10777502B2

公开(公告)日：2020-09-15

申请号：US16667911

申请日：2019-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Wei-Ting Chen

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L49/02 ,  H01L21/56 ,  H01L21/768

Abstract: A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.

公开(公告)号：US20200066631A1

公开(公告)日：2020-02-27

申请号：US16667911

申请日：2019-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Wei-Ting Chen

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L49/02 ,  H01L21/56 ,  H01L21/768

Abstract: A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.

公开(公告)号：US10157795B2

公开(公告)日：2018-12-18

申请号：US15727626

申请日：2017-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Wei-Ting Chen

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/12 ,  H01L21/84

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

公开(公告)号：US09812549B2

公开(公告)日：2017-11-07

申请号：US15257567

申请日：2016-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Chen-Hsiang Lu ,  Wei-Ting Chen ,  Yu-Cheng Liu

IPC: H01L21/3205 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L29/51

CPC classification number: H01L29/6653 ,  H01L21/28008 ,  H01L21/28247 ,  H01L21/31116 ,  H01L23/5226 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One or more formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements. The method further includes partially removing the spacer elements such that an upper portion of the recess becomes wider. In addition, the method includes forming a metal gate stack in the recess and forming a protection element over the metal gate stack to fill the recess.

公开(公告)号：US20250087533A1

公开(公告)日：2025-03-13

申请号：US18619626

申请日：2024-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsing Tsai ,  Ya-Lien Lee ,  Chih-Han Tseng ,  Kuei-Wen Huang ,  Kuan-Hung Ho ,  Ming-Uei Hung ,  Chih-Cheng Kuo ,  Yi-An Lai ,  Wei-Ting Chen

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a via in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer, where the opening exposes an upper surface of the via; selectively forming a capping layer over the upper surface of the via, where the capping layer has a curved upper surface that extends above a first upper surface of the first dielectric layer distal from the substrate; after forming the capping layer, forming a barrier layer in the opening over the capping layer and along sidewalls of the second dielectric layer exposed by the opening; and filling the opening by forming an electrically conductive material over the barrier layer.

公开(公告)号：US20230275142A1

公开(公告)日：2023-08-31

申请号：US18313190

申请日：2023-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Jui-Ping Chuang ,  Chen-Hsiang Lu ,  Yu-Cheng Liu ,  Wei-Ting Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/42372 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7848 ,  H01L29/7851 ,  H01L21/31111 ,  H01L21/76224

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.