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    Incremental multi-patterning validation
    1.
    发明授权
    Incremental multi-patterning validation 有权

    公开(公告)号：US10311195B2

    公开(公告)日：2019-06-04

    申请号：US14996796

    申请日：2016-01-15

    Applicant: Synopsys, Inc.

    Inventor： Yuli Xue ,  Weiping Fang ,  John Robert Studders ,  Byungwook Kim

    IPC: G06F17/50 ,  H01L21/84 ,  G03F1/00

    Abstract: A computer-implemented method for validating a design characterized by a multi-patterning layer is presented. The method includes receiving the multi-patterning layer in a memory of the computer when the computer is invoked to validate the design. The method further includes correcting, using the computer, a first error in a first shape of the multi-patterning layer in accordance with a first rule thereby forming a corrected layer. The method further includes incrementally validating, using the computer, a first portion of the corrected layer in accordance with the first error and a first connected component of a first graph associated with the multi-patterning layer.

    Detecting and displaying multi-patterning fix guidance
    2.
    发明授权
    Detecting and displaying multi-patterning fix guidance 有权
    检测和显示多图案定位指导

    公开(公告)号：US09384319B2

    公开(公告)日：2016-07-05

    申请号：US14459657

    申请日：2014-08-14

    Applicant: Synopsys, Inc.

    Inventor： Erdem Cilingir ,  Srini Arikati ,  Weiping Fang ,  Marco Hug

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.

    Abstract translation: 提出了一种用于验证设计的计算机实现方法。 该方法包括当计算机被调用以验证设计时，使用计算机生成不可分解成代表设计的有色图形的图形。 该方法还包括使用计算机识别与设计相关联的掩模布局中的至少一个冲突的至少一个引导，导致图形不可分解的冲突。

    DETECTING AND DISPLAYING MULTI-PATTERNING FIX GUIDANCE
    3.
    发明申请
    DETECTING AND DISPLAYING MULTI-PATTERNING FIX GUIDANCE 有权
    检测和显示多模式指南

    公开(公告)号：US20150052490A1

    公开(公告)日：2015-02-19

    申请号：US14459657

    申请日：2014-08-14

    Applicant: Synopsys, Inc.

    Inventor： Erdem Cilingir ,  Srini Arikati ,  Weiping Fang ,  Marco Hug

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.

    Abstract translation: 提出了一种用于验证设计的计算机实现方法。 该方法包括当计算机被调用以验证设计时，使用计算机生成不可分解成代表设计的有色图形的图形。 该方法还包括使用计算机识别与设计相关联的掩模布局中的至少一个冲突的至少一个引导，导致图形不可分解的冲突。

    Pattern matching using anchors during integrated circuit verification
    4.
    发明授权
    Pattern matching using anchors during integrated circuit verification 有权

    公开(公告)号：US11487930B2

    公开(公告)日：2022-11-01

    申请号：US17085727

    申请日：2020-10-30

    Applicant: Synopsys, Inc.

    Inventor： Chen Gao ,  Yuli Xue ,  Tony Tan ,  Weiping Fang

    IPC: G06F30/00 ,  G06F30/398 ,  G06F30/392 ,  G06F119/12

    Abstract: Pattern matching using anchors during integrated circuit (IC) verification is disclosed. According to one embodiment, a method includes obtaining match time estimates associated with pattern anchors of different anchor types for an IC pattern, generating revised match time estimates based on a target IC layout, and then selecting the pattern anchor associated with the shortest revised match time estimate. Then, target anchors of the same anchor type as the selected pattern anchor are generated for the target IC layout, and the target IC layout is searched for the IC pattern using the selected pattern anchor and the target anchors.

    DETECTING AND DISPLAYING MULTI-PATTERNING FIX GUIDANCE
    6.
    发明申请
    DETECTING AND DISPLAYING MULTI-PATTERNING FIX GUIDANCE 审中-公开
    检测和显示多模式指南

    公开(公告)号：US20170004251A1

    公开(公告)日：2017-01-05

    申请号：US15179890

    申请日：2016-06-10

    Applicant: Synopsys, Inc.

    Inventor： Erdem Cilingir ,  Srinivasa R. Arikati ,  Weiping Fang ,  Marco Hug

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.

    Abstract translation: 提出了一种用于验证设计的计算机实现方法。 该方法包括当计算机被调用以验证设计时，使用计算机生成不可分解成代表设计的有色图形的图形。 该方法还包括使用计算机识别与设计相关联的掩模布局中的至少一个冲突的至少一个引导，导致图形不可分解的冲突。

    AUTOMATED REPAIR METHOD AND SYSTEM FOR DOUBLE PATTERNING CONFLICTS
    7.
    发明申请
    AUTOMATED REPAIR METHOD AND SYSTEM FOR DOUBLE PATTERNING CONFLICTS 有权
    自动修复方法和系统的双重方式冲突

    公开(公告)号：US20140089868A1

    公开(公告)日：2014-03-27

    申请号：US13628002

    申请日：2012-09-26

    Applicant: SYNOPSYS, INC.

    Inventor： Paul David Friedberg ,  Tong Gao ,  Weiping Fang ,  Yang-Shan Tong

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method of performing double patterning (DPT) conflict repairs is described. In this method, even cycles adjacent to odd cycles in a layout can be identified (also called adjacent even/odd cycles herein). The identifying can include forming graph constructs of the layout. Route guidances for break-link operations and split-node operations can be prioritized for the adjacent even/odd cycles. A list including the route guidances for the break-link operations and the split-node operations can be generated. The list can be ordered based on the prioritizing.

    Abstract translation: 描述了执行双重图案化（DPT）冲突修复的方法。 在该方法中，可以识别在布局中与奇数周期相邻的偶数循环（在本文中也称为相邻偶数/奇数周期）。 识别可以包括形成布局的图形构造。 对于相邻的偶数/奇数周期，可以优先考虑断点操作和分离节点操作的路由指导。 可以生成包括断点操作和分割节点操作的路由指南的列表。 列表可以根据优先级排序。

    Automated repair method and system for double patterning conflicts
    8.
    发明授权
    Automated repair method and system for double patterning conflicts 有权
    双重图案化冲突的自动修复方法和系统

    公开(公告)号：US08701056B1

    公开(公告)日：2014-04-15

    申请号：US13628002

    申请日：2012-09-26

    Applicant: Synopsys, Inc.

    Inventor： Paul David Friedberg ,  Tong Gao ,  Weiping Fang ,  Yang-Shan Tong

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method of performing double patterning (DPT) conflict repairs is described. In this method, even cycles adjacent to odd cycles in a layout can be identified (also called adjacent even/odd cycles herein). The identifying can include forming graph constructs of the layout. Route guidances for break-link operations and split-node operations can be prioritized for the adjacent even/odd cycles. A list including the route guidances for the break-link operations and the split-node operations can be generated. The list can be ordered based on the prioritizing.

    Abstract translation: 描述了执行双重图案化（DPT）冲突修复的方法。 在该方法中，可以识别在布局中与奇数周期相邻的偶数循环（在本文中也称为相邻偶数/奇数周期）。 识别可以包括形成布局的图形构造。 对于相邻的偶数/奇数周期，可以优先考虑断点操作和分离节点操作的路由指导。 可以生成包括断点操作和分割节点操作的路由指南的列表。 列表可以根据优先级排序。

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