公开(公告)号：US20170186860A1

公开(公告)日：2017-06-29

申请号：US15098164

申请日：2016-04-13

Applicant: Synopsys, Inc.

Inventor： Hiu Y. Wong ,  Nelson de Almeida Braga ,  Rimvydas Mickevicius

IPC: H01L29/778 ,  G06F17/50 ,  H01L29/66

CPC classification number: G06F17/5072 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7786

Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.

公开(公告)号：US11152313B1

公开(公告)日：2021-10-19

申请号：US16526834

申请日：2019-07-30

Applicant: Synopsys, Inc.

Inventor： Hiu Yung Wong ,  Rimvydas Mickevicius

IPC: H01L23/00 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/861 ,  H01L29/32 ,  H01L29/66 ,  H01L21/8252 ,  H01L29/872 ,  H04L9/32

Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, a physically unclonable function (PUF) device includes a crystalline substrate and a stack of crystalline layers on top. The stack is grown epitaxially such that lattice mismatch causes threading dislocations from the substrate to the top surface of the stack. Diodes are formed on the top surface by forming anode material on the top surface of the stack, thereby forming a diode junction with a cathode region below. A diode which includes a threading dislocation has a higher leakage current than one that does not. Circuitry connected to the diodes interrogates the array and outputs binary values indicating, for each of the diodes, whether the diode includes a threading dislocation. Such binary values can be used as the PUF of the chip. This Abstract is not intended to limit the scope of the claims.

公开(公告)号：US10733348B2

公开(公告)日：2020-08-04

申请号：US16014942

申请日：2018-06-21

Applicant: SYNOPSYS, INC.

Inventor： Hiu Yung Wong ,  Nelson de Almeida Braga ,  Rimvydas Mickevicius

IPC: G06F30/392 ,  H01L29/423 ,  H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  G06F30/39 ,  G06F30/367 ,  G06F30/398

Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.

公开(公告)号：US10403625B2

公开(公告)日：2019-09-03

申请号：US16159483

申请日：2018-10-12

Applicant: Synopsys, Inc.

Inventor： Hiu Yung Wong ,  Nelson de Almeida Braga ,  Rimvydas Mickevicius

IPC: H01L29/778 ,  H01L27/085 ,  H01L29/423 ,  H01L27/088 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06

Abstract: Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. A first gate has a first tine, the first tine within the first gap, the first gap having a length of less than about 200 nm. In the first piezoelectric layer immediately beneath the second piezoelectric layer, directly beneath the first gap, stress in the dielectric layer creates a piezoelectric charge of at least about 1×1011 per cm2 of electronic charge. The first gate controls a normally off segment of the channel region. A second gate, having a length of at least 500 nm, controls a normally on segment of the channel region.

公开(公告)号：US20190148371A1

公开(公告)日：2019-05-16

申请号：US16159483

申请日：2018-10-12

Applicant: Synopsys, Inc.

Inventor： Hiu Yung Wong ,  Nelson de Almeida Braga ,  Rimvydas Mickevicius

IPC: H01L27/085 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L27/085 ,  H01L27/0883 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/7786 ,  H01L29/7787

Abstract: Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. A first gate has a first tine, the first tine within the first gap, the first gap having a length of less than about 200 nm. In the first piezoelectric layer immediately beneath the second piezoelectric layer, directly beneath the first gap, stress in the dielectric layer creates a piezoelectric charge of at least about 1×1011 per cm2 of electronic charge. The first gate controls a normally off segment of the channel region. A second gate, having a length of at least 500 nm, controls a normally on segment of the channel region.

公开(公告)号：US11348017B1

公开(公告)日：2022-05-31

申请号：US16183658

申请日：2018-11-07

Applicant: Synopsys, Inc.

Inventor： Hiu Yung Wong ,  Nelson de Almeida Braga ,  Rimvydas Mickevicius

IPC: G06N5/04 ,  G06N20/00 ,  G06F30/30 ,  G06F111/02 ,  G06F111/10

Abstract: Embodiments provide efficient, robust, and accurate programmatic prediction of optimized TCAD simulator system settings for future simulation executions to be performed by a TCAD simulation system.

公开(公告)号：US10128232B2

公开(公告)日：2018-11-13

申请号：US15599984

申请日：2017-05-19

Applicant: Synopsys, Inc.

Inventor： Hiu Yung Wong ,  Nelson de Almeida Braga ,  Rimvydas Mickevicius

IPC: H01L29/778 ,  H01L27/085 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088

Abstract: Roughly described, a heterojunction field effect transistor device includes a first piezoelectric layer supporting a channel region, a second piezoelectric layer over the first, and a source and drain. A dielectric layer over the second piezoelectric layer electrically separates the source and drain, and has a plurality of segments, two of them separated by a first gap. A first gate has a first tine, the first tine within the first gap, the first gap having a length of less than about 200 nm. In the first piezoelectric layer immediately beneath the second piezoelectric layer, directly beneath the first gap, stress in the dielectric layer creates a piezoelectric charge of at least about 1×1011 per cm2 of electronic charge. The first gate controls a normally off segment of the channel region. A second gate, having a length of at least 500 nm, controls a normally on segment of the channel region.

公开(公告)号：US20180300443A1

公开(公告)日：2018-10-18

申请号：US16014942

申请日：2018-06-21

Applicant: SYNOPSYS, INC.

Inventor： Hiu Yung Wong ,  Nelson de Almeida Braga ,  Rimvydas Mickevicius

IPC: G06F17/50 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/06

Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.

公开(公告)号：US10777638B1

公开(公告)日：2020-09-15

申请号：US16239403

申请日：2019-01-03

Applicant: Synopsys, Inc.

Inventor： Hiu Yung Wong ,  Nelson de Almeida Braga ,  Rimvydas Mickevicius

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/812 ,  H01L29/417 ,  H01L29/778

Abstract: Roughly described, an integrated circuit device includes a semiconductor having an overall length. In successively adjacent longitudinal sequence, the semiconductor includes first, second and third lengths all having a same first conductivity type. One end of the longitudinal sequence (the end adjacent to the first length) can be referred to a source end of the sequence, and the other end (adjacent to the third length) can be referred to as a drain end. Overlying the second length is a first gate conductor, which defines a first body region. Overlying a cascode portion of the third length is a second gate conductor, which defines a second body region. The second gate conductor preferably is longitudinally continuous with the first gate conductor, but if not, then the two are connected together by other conductors. The first body region is recessed relative to the first and third lengths of the semiconductor.

公开(公告)号：US10769339B1

公开(公告)日：2020-09-08

申请号：US16535523

申请日：2019-08-08

Applicant: Synopsys, Inc.

Inventor： Hiu Yung Wong ,  Rimvydas Mickevicius

IPC: G06F30/367 ,  G06F30/392 ,  G06F111/04 ,  G06F111/10 ,  G06F111/20

Abstract: An improved local modeling function for estimating band-to-band tunneling currents RBBT in nanodevices and other low-voltage circuit elements during TCAD simulation, the model being represented by the equation: R B ⁢ B ⁢ T = - B ⁢  F  σ = exp ⁡ ( - F 0  F  ) ⁢ g where terms B, F, F0 and σ correspond to conventional terms used in Hurkx-based equations, and the term g is an exponential factor determined by the equation: g = ( F - F 1 F 1 ) 1 . 5 where the term F1 is the built-in electric field at a selected cell/point determined by the equation: F 1 = max ⁡ ( F ˜ 1 , C ⁢ 2 ⁢ q ⁢ E g ⁢ N n ⁢ e ⁢ t ɛ ) where {tilde over (F)}1 is the built-in electric field at zero bias, q is fundamental electronic charge, C is a fitting parameter, Eg is bandgap, Nnet is doping concentration, and E is dielectric constant. At low applied fields (F˜F0) the factor g biases the improved model toward the zero-field/zero-current origin in a way that closely matches non-local model results. At higher applied fields the factor g has less influence and the model is controlled by the conventional terms.