公开(公告)号：US20130268817A1

公开(公告)日：2013-10-10

申请号：US13910888

申请日：2013-06-05

Applicant: Synopsys, Inc.

Inventor： Peter Wohl ,  John A. Waicukauski ,  Frederic J. Neuveux

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318547

Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.

Abstract translation: 扫描测试和扫描压缩是实现成本降低和出货质量的关键。 更复杂设计中的新缺陷类型需要增加压缩。 然而，未知（X）值的增加的密度降低了有效压缩。 扫描压缩方法可以为未知值的任何密度实现非常高的压缩和全覆盖。 所描述的技术可以完全集成在测试设计（DFT）和自动测试模式生成（ATPG）流程中。 在工业设计中使用这些技术的结果表明与其他方法相比是一致和可预测的优势。

公开(公告)号：US09404972B2

公开(公告)日：2016-08-02

申请号：US14875019

申请日：2015-10-05

Applicant: Synopsys, Inc.

Inventor： Peter Wohl ,  John A Waicukauski ,  Emil Gizdarski ,  Wolfgang Meyer ,  Andrea Costa

IPC: G06F17/50 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G06F17/5022 ,  G06F17/5081

Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.

Abstract translation: 分析用于检测半导体芯片中的故障的模式以确定设计中的逻辑子集，其中基于该设计制造的半导体芯片在该子集中包含故障。 可以预先计算半导体芯片的部分，以基于模式识别逻辑的关键子部分，该部分存储在计算机可读文件中。 使用截断秩序仿真对逻辑子部分执行良好的机器仿真。 将结果与物理半导体芯片的测试结果进行比较。

公开(公告)号：US09157961B2

公开(公告)日：2015-10-13

申请号：US13831617

申请日：2013-03-15

Applicant: Synopsys, Inc.

Inventor： Peter Wohl ,  John A. Waicukauski ,  Frederic J. Neuveux ,  Gregory A. Maston

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318547

Abstract: A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual loaded in a single CODEC. This sharing of seeds, exploits the hierarchical nature of large designs with many PRPGs, provides a second compression. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage, diagnosability, and performance.

Abstract translation: 扫描测试系统和技术将CARE位和X控制输入数据压缩到PRPG种子中，从而提供第一压缩。 扫描测试系统包括多个压缩器和解压缩器结构（CODEC）。 每个设计块包括至少一个CODEC。 指令解码单元（IDU）接收扫描输入并确定从扫描输入中提取的种子是否被广播加载在CODEC中，组播加载在编解码器的子集中，或者加载在单个编解码器中的个体。 这种共享种子，利用许多PRPG的大型设计的层次性，提供了第二次压缩。 大型工业设计的结果表明显着的数据和循环压缩增加，同时保持测试覆盖率，可诊断性和性能。

公开(公告)号：US20140281774A1

公开(公告)日：2014-09-18

申请号：US13831617

申请日：2013-03-15

Applicant: SYNOPSYS, INC.

Inventor： Peter Wohl ,  John A. Waicukauski ,  Frederic J. Neuveux ,  Gregory A. Maston

IPC: G01R31/3177

CPC classification number: G01R31/318547

Abstract: A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual loaded in a single CODEC. This sharing of seeds, exploits the hierarchical nature of large designs with many PRPGs, provides a second compression. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage, diagnosability, and performance.

Abstract translation: 扫描测试系统和技术将CARE位和X控制输入数据压缩到PRPG种子中，从而提供第一压缩。 扫描测试系统包括多个压缩器和解压缩器结构（CODEC）。 每个设计块包括至少一个CODEC。 指令解码单元（IDU）接收扫描输入并确定从扫描输入中提取的种子是否被广播加载在CODEC中，组播加载在编解码器的子集中，或者加载在单个编解码器中的个体。 这种共享种子，利用许多PRPG的大型设计的层次性，提供了第二次压缩。 大型工业设计的结果表明显着的数据和循环压缩增加，同时保持测试覆盖率，可诊断性和性能。

公开(公告)号：US20180156869A1

公开(公告)日：2018-06-07

申请号：US15450962

申请日：2017-03-06

Applicant: Synopsys, Inc.

Inventor： Peter Wohl ,  John Waicukauski

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/318342

Abstract: A method for generating scan-based test patterns for an integrated circuit design includes, in a computer system, generating a number of current interval patterns for the integrated circuit design in a current pattern generation interval. The current interval patterns can be augmented to satisfy observe needs of a previous interval pattern generated in a previous pattern generation interval. Observe needs of the current interval patterns are stored in association with the current interval patterns. The current interval patterns are linked respectively to P streams of test patterns. The current pattern generation interval is subsequent to the previous pattern generation interval. The method includes simulating the current interval patterns to identify observable scan cells in the integrated circuit design, linking the P streams of test patterns into a single stream of test patterns, and storing the single stream of test patterns in a computer readable medium.

公开(公告)号：US09171123B2

公开(公告)日：2015-10-27

申请号：US14015982

申请日：2013-08-30

Applicant: Synopsys, Inc.

Inventor： Peter Wohl ,  John A Waicukauski ,  Emil Gizdarski ,  Wolfgang Meyer ,  Andrea Costa

IPC: G06F17/50

CPC classification number: G01R31/3177 ,  G06F17/5022 ,  G06F17/5081

Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.

Abstract translation: 分析用于检测半导体芯片中的故障的模式以确定设计中的逻辑子集，其中基于该设计制造的半导体芯片在该子集中包含故障。 可以预先计算半导体芯片的部分，以基于模式识别逻辑的关键子部分，该部分存储在计算机可读文件中。 使用截断秩序仿真对逻辑子部分执行良好的机器仿真。 将结果与物理半导体芯片的测试结果进行比较。

公开(公告)号：US12277372B2

公开(公告)日：2025-04-15

申请号：US17721264

申请日：2022-04-14

Applicant: Synopsys, Inc.

Inventor： Peter Wohl ,  John A. Waicukauski

IPC: G06F30/3308 ,  G06F30/20 ,  G06F30/367 ,  G06F30/396 ,  G06F30/398

Abstract: A system and method generates test patterns for simulating a circuit design. Generating the test patterns includes determining clock data of the circuit design. The clock data is determined by determining a first clock signal pair from clock signals, and determining a disturb cell based on the first clock signal pair. The disturb cell is electrically coupled to a first clock signal of the first clock signal pair, and to a second cell. The second cell is electrically coupled to a second clock signal of the first clock signal pair, and an input of the second cell is electrically coupled to an output of the disturb cell. A first test pattern is generated based on the clock data and is output to a memory to be used in simulating a circuit design.

公开(公告)号：US10908213B1

公开(公告)日：2021-02-02

申请号：US16586652

申请日：2019-09-27

Applicant: Synopsys, Inc.

Inventor： Emil Gizdarski ,  Peter Wohl ,  John A. Waicukauski

IPC: G01R31/28 ,  G01R31/3185

Abstract: A proposed linear time compactor (LTC) with a means of significantly reducing the X-masking effect for designs with X's and supports high levels of test data compression where: 1) The LTC consists of two parts that are unloaded into a tester through an output serializer. 2) The first part is unloaded per t shift cycles while the second part is unloaded once per test pattern. 3) One part of the LTC divides scan chains into groups such that X-masking effect between groups of scan chains is impossible. 4) One part of LTC divides shift cycles into groups such that X-masking effect between groups of shift cycles is impossible. Consequently, the X-masking effect in the proposed LTC is significantly reduced.

公开(公告)号：US10346557B2

公开(公告)日：2019-07-09

申请号：US15450962

申请日：2017-03-06

Applicant: Synopsys, Inc.

Inventor： Peter Wohl ,  John Waicukauski

IPC: G01R31/00 ,  G06F17/50 ,  G01R31/3183

Abstract: A method for generating scan-based test patterns for an integrated circuit design includes, in a computer system, generating a number of current interval patterns for the integrated circuit design in a current pattern generation interval. The current interval patterns can be augmented to satisfy observe needs of a previous interval pattern generated in a previous pattern generation interval. Observe needs of the current interval patterns are stored in association with the current interval patterns. The current interval patterns are linked respectively to P streams of test patterns. The current pattern generation interval is subsequent to the previous pattern generation interval. The method includes simulating the current interval patterns to identify observable scan cells in the integrated circuit design, linking the P streams of test patterns into a single stream of test patterns, and storing the single stream of test patterns in a computer readable medium.

公开(公告)号：US08645780B2

公开(公告)日：2014-02-04

申请号：US13910888

申请日：2013-06-05

Applicant: Synopsys, Inc.

Inventor： Peter Wohl ,  John A. Waicukauski ,  Frederic J. Neuveux

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/318547

Abstract: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.

Abstract translation: 扫描测试和扫描压缩是实现成本降低和出货质量的关键。 更复杂设计中的新缺陷类型需要增加压缩。 然而，未知（X）值的增加的密度降低了有效压缩。 扫描压缩方法可以为未知值的任何密度实现非常高的压缩和全覆盖。 所描述的技术可以完全集成在测试设计（DFT）和自动测试模式生成（ATPG）流程中。 在工业设计中使用这些技术的结果表明与其他方法相比是一致和可预测的优势。