公开(公告)号：US10826469B2

公开(公告)日：2020-11-03

申请号：US16795456

申请日：2020-02-19

Applicant: Synopsys, Inc.

Inventor： Manish Srivastava ,  Pradip Subhana Jadhav

IPC: H03K3/356 ,  H03K3/012

Abstract: A True Single Phase Clock (TSPC) latch design with symmetrical input data paths. A first input data path includes: a first NMOS transistor coupling a gate of a first PMOS transistor to VSS in response to a rising input data signal, and a second PMOS transistor having a gate coupled to a logic low (VSS) input clock signal, whereby the first and second PMOS transistors turn on to couple a data input node to VDD. A second input data path includes: a third PMOS transistor having a gate coupled to a falling input data signal (VSS), a fourth PMOS transistor having a gate coupled to a logic low (VSS) input clock signal, whereby the third and fourth PMOS transistors turn on to couple a gate of a second NMOS transistor to VDD, whereby the second NMOS transistor turns on to couple the data input node to VSS.

公开(公告)号：US20160301391A1

公开(公告)日：2016-10-13

申请号：US14682413

申请日：2015-04-09

Applicant: Synopsys, Inc.

Inventor： Manish Srivastava ,  Basannagouda Somanath Reddy

IPC: H03K3/012 ,  H03K3/3562 ,  H03K5/24

CPC classification number: H03K3/012 ,  H03K3/35625 ,  H03K5/24

Abstract: A multi-bit flip-flop (MBFF) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The MBFF also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal. The local control signals are provided to the input data selection circuits, and exclusively control the input data selection circuits to route either the input data signal or the scan input data signal as a master data bit, reducing transistor requirements. Local clock signals may be generated by the local signal generation circuit in response to the global clock signal, and may exclusively control data transfer within the flip-flops, improving setup time.

Abstract translation: 多位触发器（MBFF）包括多个1位触发器，每个触发器具有接收数据信号和扫描数据信号的输入数据选择电路。 MBFF还包括接收全局时钟信号和全局扫描使能信号的本地信号发生电路，并且作为响应，提供本地控制信号，其中每个本地控制信号响应于全局时钟信号和 全局扫描使能信号。 本地控制信号被提供给输入数据选择电路，并专门地控制输入数据选择电路以将输入数据信号或扫描输入数据信号作为主数据位进行路由，从而减少了晶体管的要求。 本地时钟信号可以由本地信号发生电路响应于全局时钟信号产生，并且可以排他地控制触发器内的数据传输，从而改善建立时间。

公开(公告)号：US20200274525A1

公开(公告)日：2020-08-27

申请号：US16795456

申请日：2020-02-19

Applicant: Synopsys, Inc.

Inventor： Manish Srivastava ,  Pradip Subhana Jadhav

IPC: H03K3/356 ,  H03K3/012

Abstract: A True Single Phase Clock (TSPC) latch design with symmetrical input data paths. A first input data path includes: a first NMOS transistor coupling a gate of a first PMOS transistor to VSS in response to a rising input data signal, and a second PMOS transistor having a gate coupled to a logic low (VSS) input clock signal, whereby the first and second PMOS transistors turn on to couple a data input node to VDD. A second input data path includes: a third PMOS transistor having a gate coupled to a falling input data signal (VSS), a fourth PMOS transistor having a gate coupled to a logic low (VSS) input clock signal, whereby the third and fourth PMOS transistors turn on to couple a gate of a second NMOS transistor to VDD, whereby the second NMOS transistor turns on to couple the data input node to VSS.

公开(公告)号：US09729128B2

公开(公告)日：2017-08-08

申请号：US14682413

申请日：2015-04-09

Applicant: Synopsys, Inc.

Inventor： Manish Srivastava ,  Basannagouda Somanath Reddy

IPC: H03K3/02 ,  H03K3/012 ,  H03K5/24 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35625 ,  H03K5/24

Abstract: A multi-bit flip-flop (MBFF) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The MBFF also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal. The local control signals are provided to the input data selection circuits, and exclusively control the input data selection circuits to route either the input data signal or the scan input data signal as a master data bit, reducing transistor requirements. Local clock signals may be generated by the local signal generation circuit in response to the global clock signal, and may exclusively control data transfer within the flip-flops, improving setup time.