公开(公告)号：US08949757B2

公开(公告)日：2015-02-03

申请号：US13868096

申请日：2013-04-22

Applicant: Synopsys, Inc.

Inventor： Levent Oktem

IPC: G06F17/50

CPC classification number: G06F17/5059 ,  G06F17/505

Abstract: A method and apparatus to design a circuit is described. In on embodiment, the method comprises selecting a target clock for a design of the circuit, and determining a plurality of latencies for a portion of the circuit. The method further comprises determining a representation of a data flow graph for the portion of the circuit, the data flow graph having a first node connected with a second node by a number of extra delays determined based on the target clock and the plurality of latencies, the first node and second node representing paths that start from and end in registers in the portion of the circuit, the first node connecting to a node between a first input of the portion of the circuit and an input of a register of the portion of the circuit. The method continues to retime the design for the circuit to operate at the target clock based on the representation of the data flow graph, wherein at least one of the selecting, determining, and retiming is performed by a processor.

Abstract translation: 描述了一种设计电路的方法和装置。 在实施例中，该方法包括为电路设计选择目标时钟，以及确定电路的一部分的多个延迟。 该方法还包括确定电路部分的数据流图的表示，数据流图具有与第二节点连接的第一节点多个基于目标时钟和多个延迟确定的额外延迟， 所述第一节点和第二节点表示从所述电路的所述部分中的寄存器开始和结束的路径，所述第一节点连接到所述电路的所述部分的第一输入端与所述电路的所述部分的寄存器的输入之间的节点 电路。 该方法继续基于数据流图的表示来重新计算电路的设计以在目标时钟下操作，其中由处理器执行选择，确定和重新定时中的至少一个。

公开(公告)号：US08645882B2

公开(公告)日：2014-02-04

申请号：US13658760

申请日：2012-10-23

Applicant: Synopsys, Inc.

Inventor： Mustafa Ispir ,  Levent Oktem

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06N3/006

Abstract: A method for designing an integrated circuit is described. The method comprises converting behavioral descriptions of the integrated circuit to register transfer level (RTL) descriptions. The method comprises at least one of the behavioral descriptions including frame synthesis with an input frame and a corresponding output frame. In one embodiment, the method further comprises providing at least two solutions for performing partial and complete operations for simulations as hardware component combinations, associating each solution with a cost, and selecting the solution with the lowest cost as the hardware component combination for a final design of the integrated circuit.

Abstract translation: 描述了一种用于设计集成电路的方法。 该方法包括将集成电路的行为描述转换为注册传输级（RTL）描述。 该方法包括至少一个行为描述，包括具有输入帧的帧合成和相应的输出帧。 在一个实施例中，该方法还包括提供至少两个解决方案，用于执行模拟的部分和完全操作作为硬件组件组合，将每个解决方案与成本相关联，并且以最低成本选择最终成本的解决方案作为最终设计的硬件组件组合 的集成电路。

公开(公告)号：US20130239081A1

公开(公告)日：2013-09-12

申请号：US13868096

申请日：2013-04-22

Applicant: SYNOPSYS, INC.

Inventor： Levent Oktem

IPC: G06F17/50

CPC classification number: G06F17/5059 ,  G06F17/505

Abstract: A method and apparatus to design a circuit is described. In on embodiment, the method comprises selecting a target clock for a design of the circuit, and determining a plurality of latencies for a portion of the circuit. The method further comprises determining a representation of a data flow graph for the portion of the circuit, the data flow graph having a first node connected with a second node by a number of extra delays determined based on the target clock and the plurality of latencies, the first node and second node representing paths that start from and end in registers in the portion of the circuit, the first node connecting to a node between a first input of the portion of the circuit and an input of a register of the portion of the circuit. The method continues to retime the design for the circuit to operate at the target clock based on the representation of the data flow graph, wherein at least one of the selecting, determining, and retiming is performed by a processor.

Abstract translation: 描述了一种设计电路的方法和装置。 在实施例中，该方法包括为电路设计选择目标时钟，以及确定电路的一部分的多个延迟。 该方法还包括确定电路部分的数据流图的表示，数据流图具有与第二节点连接的第一节点多个基于目标时钟和多个延迟确定的额外延迟， 所述第一节点和第二节点表示从所述电路的所述部分中的寄存器开始和结束的路径，所述第一节点连接到所述电路的所述部分的第一输入端与所述电路的所述部分的寄存器的输入之间的节点 电路。 该方法继续基于数据流图的表示来重新计算电路的设计以在目标时钟下操作，其中由处理器执行选择，确定和重新定时中的至少一个。