公开(公告)号：US08472267B2

公开(公告)日：2013-06-25

申请号：US13164382

申请日：2011-06-20

Applicant: Abhijeet R. Tanpure ,  Steven C. Sullivan ,  William V. Miller ,  Jason A. Frerich

Inventor： Abhijeet R. Tanpure ,  Steven C. Sullivan ,  William V. Miller ,  Jason A. Frerich

IPC: G11C7/00

CPC classification number: G11C8/08 ,  G11C5/025

Abstract: Sense amplifiers in a memory may be activated and deactivated. In one embodiment, a processor may include a memory. The memory may include a number of sense amplifiers. Based on a late arriving address bit of an address used to access data from the memory, a sense amplifier may be activated while another sense amplifier may be deactivated.

Abstract translation: 存储器中的感测放大器可以被激活并被去激活。 在一个实施例中，处理器可以包括存储器。 存储器可以包括多个读出放大器。 基于用于从存储器访问数据的地址的晚到地址位，可以激活读出放大器，而另一个读出放大器可以被去激活。

公开(公告)号：US5530676A

公开(公告)日：1996-06-25

申请号：US379807

申请日：1995-01-27

Applicant: Steven C. Sullivan ,  Michael L. Brauer

Inventor： Steven C. Sullivan ,  Michael L. Brauer

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/00

CPC classification number: G11C8/18 ,  G11C7/22

Abstract: A clock signal (202) is received, wherein the rising edge of the clock signal (202) controls an operation of a memory cell (224) of a memory circuit (200). Address information (204) is received and predecoded prior to the rising edge of the clock signal (202) to produce a row select signal (210). A control signal (201), which is received prior to the rising edge of the clock signal, determines whether the operation is a read operation or a write operation. If the operation is a write operation, new data information (218) is received a data delay after the rising edge of the clock signal (202); the row select signal (210) is delayed such that the memory cell (224) is selected at least a data delay after the rising edge of the clock signal (202); and the new data information (218) is written to the memory cell (224).

Abstract translation: 接收时钟信号（202），其中时钟信号（202）的上升沿控制存储器电路（200）的存储单元（224）的操作。 地址信息（204）在时钟信号（202）的上升沿之前被接收并预解码，以产生行选择信号（210）。 在时钟信号的上升沿之前接收的控制信号（201）确定操作是读取操作还是写入操作。 如果操作是写入操作，则在时钟信号（202）的上升沿之后接收数据延迟的新数据信息（218）。 行选择信号（210）被延迟使得在时钟信号（202）的上升沿之后至少选择存储单元（224）至少数据延迟; 并将新的数据信息（218）写入存储单元（224）。

公开(公告)号：US08432756B1

公开(公告)日：2013-04-30

申请号：US13275920

申请日：2011-10-18

Applicant: Steven C. Sullivan ,  William V. Miller

Inventor： Steven C. Sullivan ,  William V. Miller

IPC: G11C7/00

CPC classification number: G11C7/1075

Abstract: A dual port memory includes a mechanism for preventing collisions. The memory includes dual port bit cells arranged in rows and columns and each bit cell stores a data bit. The memory also includes a wordline unit that may provide a respective write wordline signal and a respective read wordline signal to each row of bit cells. The wordline unit may also selectively inhibit the read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row.

Abstract translation: 双端口存储器包括用于防止冲突的机构。 存储器包括以行和列布置的双端口位单元，并且每个位单元存储数据位。 存储器还包括字线单元，其可以向每行位单元提供相应的写入字线信号和相应的读取字线信号。 字线单元还可以基于指示是否对给定行执行写入操作的地址信息来选择性地禁止给定行的读取字线信号。

公开(公告)号：US06608789B2

公开(公告)日：2003-08-19

申请号：US10027547

申请日：2001-12-21

Applicant: Steven C. Sullivan ,  Perry H. Pelley ,  George P. Hoekstra

Inventor： Steven C. Sullivan ,  Perry H. Pelley ,  George P. Hoekstra

IPC: G11C700

CPC classification number: G11C7/065

Abstract: A sense amplifier (40) uses a body shorting device (60) to selectively electrically short circuit the bodies of two transistors (44, 48) that function as a differential sensing pair. Equalization of charge injected into the bodies functions to minimize offset voltage between the two bodies. The body shorting device selectively shorts the bodies in response to a body control signal after a sense operation and after asserting a precharging signal to initiate precharging of the sense amplifier's outputs.

Abstract translation: 读出放大器（40）使用主体短路装置（60）来选择性地使作为差分感测对的两个晶体管（44,48）的主体电短路。 注入到体内的电荷的均衡起到使两个物体之间的失调电压最小化的作用。 身体短路装置在感测操作之后并且在确定预充电信号以启动感测放大器的输出的预充电之后，响应于身体控制信号选择性地短路身体。

公开(公告)号：US20130091329A1

公开(公告)日：2013-04-11

申请号：US13270653

申请日：2011-10-11

Applicant: Steven C. Sullivan

Inventor： Steven C. Sullivan

IPC: G06F12/08 ,  G11C29/04 ,  G11C7/06

CPC classification number: G11C29/84

Abstract: A memory column redundancy mechanism includes a memory having a number of data output ports each configured to output one data bit of a data element. The memory also includes a number of memory columns each connected to a corresponding respective data port. Each memory column includes a plurality of bit cells that are coupled to a corresponding sense amplifier that may differentially output a respective data bit from the plurality of bit cells on an output signal and a complemented output signal. The memory further includes an output selection unit that may select as the output data bit for a given data output port, one of the output signal of the sense amplifier associated with the given data output port or the complemented output signal of the sense amplifier associated with an adjacent data output port dependent upon a respective shift signal for each memory column.

Abstract translation: 存储器列冗余机构包括具有多个数据输出端口的存储器，每个数据输出端口被配置为输出数据元素的一个数据位。 存储器还包括各自连接到相应的相应数据端口的多个存储器列。 每个存储器列包括耦合到对应的读出放大器的多个位单元，其可以在输出信号和补码输出信号上差分地输出相应的数据位与多个位单元。 存储器还包括输出选择单元，其可以选择给定数据输出端口的输出数据位，与给定数据输出端口相关联的读出放大器的输出信号之一或与该数据输出端口相关联的读出放大器的补码输出信号 取决于每个存储器列的相应移位信号的相邻数据输出端口。

公开(公告)号：US5301163A

公开(公告)日：1994-04-05

申请号：US830768

申请日：1992-02-03

Applicant: Robert M. Reinschmidt ,  Steven C. Sullivan

Inventor： Robert M. Reinschmidt ,  Steven C. Sullivan

IPC: G11C11/415 ,  G11C8/10 ,  G11C11/413 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C8/10

Abstract: A selection circuit for a bipolar ECL memory having memory cell connected to cell selection lines and, more particularly, to upper and lower wordlines. The circuit includes a line driver connected to the upper wordline, an input stage for controlling the line driver to activate the upper wordline connected thereto in response to an address signal, and a switching device responsive to the input stage for applying a discharging current to the lower word line to speed up deactivation of the memory cell in response to a change in the address signal. In one embodiment, the line driver is also turned on at an increased rate for a limited time following application of the address signal to speed up the activation of the line.

Abstract translation: 一种用于具有连接到单元选择线的存储单元的双极ECL存储器的选择电路，更具体地，涉及上，下字线。 电路包括连接到上部字线的线路驱动器，用于控制线路驱动器以响应于地址信号来激活与其连接的上部字线的输入级，以及响应于输入级的施加放电电流的开关装置， 较低的字线，以响应于地址信号的变化而加速对存储器单元的去激活。 在一个实施例中，在施加地址信号以加速线路的激活之后，线路驱动器也以增加的速率接通有限的时间。

公开(公告)号：US08693262B2

公开(公告)日：2014-04-08

申请号：US13270653

申请日：2011-10-11

Applicant: Steven C. Sullivan

Inventor： Steven C. Sullivan

IPC: G11C7/00

CPC classification number: G11C29/84

Abstract: A memory column redundancy mechanism includes a memory having a number of data output ports each configured to output one data bit of a data element. The memory also includes a number of memory columns each connected to a corresponding respective data port. Each memory column includes a plurality of bit cells that are coupled to a corresponding sense amplifier that may differentially output a respective data bit from the plurality of bit cells on an output signal and a complemented output signal. The memory further includes an output selection unit that may select as the output data bit for a given data output port, one of the output signal of the sense amplifier associated with the given data output port or the complemented output signal of the sense amplifier associated with an adjacent data output port dependent upon a respective shift signal for each memory column.

Abstract translation: 存储器列冗余机构包括具有多个数据输出端口的存储器，每个数据输出端口被配置为输出数据元素的一个数据位。 存储器还包括各自连接到相应的相应数据端口的多个存储器列。 每个存储器列包括耦合到对应的读出放大器的多个位单元，其可以在输出信号和补码输出信号上差分地输出相应的数据位与多个位单元。 存储器还包括输出选择单元，其可以选择给定数据输出端口的输出数据位，与给定数据输出端口相关联的读出放大器的输出信号之一或与该数据输出端口相关联的读出放大器的补码输出信号 取决于每个存储器列的相应移位信号的相邻数据输出端口。

公开(公告)号：US20130094313A1

公开(公告)日：2013-04-18

申请号：US13275920

申请日：2011-10-18

Applicant: Steven C. Sullivan ,  William V. Miller

Inventor： Steven C. Sullivan ,  William V. Miller

IPC: G11C7/00

CPC classification number: G11C7/1075

Abstract: A dual port memory includes a mechanism for preventing collisions. The memory includes dual port bit cells arranged in rows and columns and each bit cell stores a data bit. The memory also includes a wordline unit that may provide a respective write wordline signal and a respective read wordline signal to each row of bit cells. The wordline unit may also selectively inhibit the read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row.

Abstract translation: 双端口存储器包括用于防止冲突的机构。 存储器包括以行和列布置的双端口位单元，并且每个位单元存储数据位。 存储器还包括字线单元，其可以向每行位单元提供相应的写入字线信号和相应的读取字线信号。 字线单元还可以基于指示是否对给定行执行写入操作的地址信息来选择性地禁止给定行的读取字线信号。

公开(公告)号：US06581140B1

公开(公告)日：2003-06-17

申请号：US09609749

申请日：2000-07-03

Applicant: Steven C. Sullivan ,  Michael D. Snyder ,  Magnus K. Bruce

Inventor： Steven C. Sullivan ,  Michael D. Snyder ,  Magnus K. Bruce

IPC: G06F1200

CPC classification number: G06F12/0864 ,  G06F2212/6082

Abstract: A system provides a method and apparatus for accessing information in a cache in a data processing system. The system optimizes a speed-critical path within the cache system by using a prediction scheme. The prediction scheme subdivides the address range of address bits and compares the portions separately. A comparison of a critical portion of the address, along with a prediction bit, are used to generate a prediction.

Abstract translation: 一种系统提供用于访问数据处理系统中的高速缓存中的信息的方法和装置。 该系统通过使用预测方案来优化缓存系统内的速度关键路径。 预测方式细分地址位的地址范围，并分别比较。 使用地址的关键部分与预测位的比较来生成预测。

公开(公告)号：US08570827B2

公开(公告)日：2013-10-29

申请号：US13164306

申请日：2011-06-20

Applicant: Steven C. Sullivan ,  Abhijeet R. Tanpure ,  William V. Miller ,  Ben D. Jarrett

Inventor： Steven C. Sullivan ,  Abhijeet R. Tanpure ,  William V. Miller ,  Ben D. Jarrett

IPC: G11C8/08

CPC classification number: G11C8/08 ,  G11C5/025

Abstract: Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream components may be activated while another wordline and downstream components may be deactivated.

Abstract translation: 可以独立地激活和去激活存储器中的可控阵列。 在一个实施例中，处理器可以包括存储器。 存储器可以是具有独立可选阵列的解交织存储器。 基于用于从存储器访问数据的地址的地址位，可以激活字线和下游组件，而可以停用另一个字线和下游组件。