公开(公告)号：US20150017795A1

公开(公告)日：2015-01-15

申请号：US14501536

申请日：2014-09-30

Applicant: Spansion LLC

Inventor： Ching-Huang Lu ,  Simon Siu-Sing Chan ,  Hidehiko Shiraiwa ,  Lei Xue

IPC: H01L27/115 ,  H01L21/265 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/11568 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/32053 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66833 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

Abstract translation: 使用与存储器件中底层衬底不相干的硅化位线触点的方法。 该方法提供了利用从与氧化物 - 氮化物 - 氧化物（ONO）氮化物边缘自对准的方法在位线接触区域中形成硅化物的方法。 该方法的另一个好处是可以消除位线接触注入和快速温度退火过程。 这种方法适用于嵌入式闪存，集成高密度设备和高级逻辑过程。

公开(公告)号：US09252154B2

公开(公告)日：2016-02-02

申请号：US14501536

申请日：2014-09-30

Applicant: Spansion LLC

Inventor： Ching-Huang Lu ,  Simon Siu-Sing Chan ,  Hidehiko Shiraiwa ,  Lei Xue

IPC: H01L23/02 ,  H01L27/115 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3205

CPC classification number: H01L27/11568 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/32053 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66833 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

Abstract translation: 使用与存储器件中底层衬底不相干的硅化位线触点的方法。 该方法提供了利用从与氧化物 - 氮化物 - 氧化物（ONO）氮化物边缘自对准的方法在位线接触区域中形成硅化物的方法。 该方法的另一个好处是可以消除位线接触注入和快速温度退火过程。 这种方法适用于嵌入式闪存，集成高密度设备和高级逻辑过程。

公开(公告)号：US09252026B2

公开(公告)日：2016-02-02

申请号：US14207303

申请日：2014-03-12

Applicant: Spansion LLC

Inventor： Rinji Sugino ,  Lei Xue ,  Ching-Huang Lu ,  Simon Chan

IPC: H01L21/76 ,  H01L21/324 ,  H01L21/764 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/3247 ,  H01L21/76224 ,  H01L21/764 ,  H01L29/0684 ,  H01L29/161

Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.

Abstract translation: 本文公开了一种用于在高密度集成电路（IC）中的紧密间隔的器件之间提供电隔离的系统和方法。 还讨论了包括衬底中的衬底，第一器件，第二器件和埋入沟槽的集成电路（IC）及其制造方法。 埋置的沟槽位于第一和第二器件之间，并且可以用电介质材料填充。 或者，埋入的沟槽包含空气。 公开了一种使用氢退火来形成埋入沟槽的方法。

公开(公告)号：US08866213B2

公开(公告)日：2014-10-21

申请号：US13753676

申请日：2013-01-30

Applicant: Spansion LLC

Inventor： Ching-Huang Lu ,  Simon Siu-Sing Chan ,  Hidehiko Shiraiwa ,  Lei Xue

IPC: H01L21/20 ,  H01L29/792 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/28282 ,  H01L21/32053 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66833 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

Abstract translation: 使用与存储器件中底层衬底不相干的硅化位线触点的方法。 该方法提供了利用从与氧化物 - 氮化物 - 氧化物（ONO）氮化物边缘自对准的方法在位线接触区域中形成硅化物的方法。 该方法的另一个好处是可以消除位线接触注入和快速温度退火过程。 这种方法适用于嵌入式闪存，集成高密度设备和高级逻辑过程。

公开(公告)号：US20150262838A1

公开(公告)日：2015-09-17

申请号：US14207303

申请日：2014-03-12

Applicant: Spansion LLC

Inventor： Rinji Sugino ,  Lei Xue ,  Ching-Huang Lu ,  Simon Chan

IPC: H01L21/324 ,  H01L21/762 ,  H01L29/06 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/3247 ,  H01L21/76224 ,  H01L21/764 ,  H01L29/0684 ,  H01L29/161

Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a buried trench in the substrate and a method of fabricating the same are also discussed. The buried trench is positioned between first and second devices and may be filled with dielectric material. Alternatively, the buried trench contains air. A method of using Hydrogen annealing to create the buried trench is disclosed.

Abstract translation: 本文公开了一种用于在高密度集成电路（IC）中的紧密间隔的器件之间提供电隔离的系统和方法。 还讨论了包括衬底中的衬底，第一器件，第二器件和埋入沟槽的集成电路（IC）及其制造方法。 埋置的沟槽位于第一和第二器件之间，并且可以用电介质材料填充。 或者，埋入的沟槽包含空气。 公开了一种使用氢退火来形成埋入沟槽的方法。