公开(公告)号：US11979155B2

公开(公告)日：2024-05-07

申请号：US18177558

申请日：2023-03-02

Applicant: SOCIONEXT INC.

Inventor： Masahisa Iida ,  Masahiro Gion

IPC: H03K3/356 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K3/356017 ,  H03K19/00315 ,  H03K19/018507

Abstract: A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.

公开(公告)号：US12274090B2

公开(公告)日：2025-04-08

申请号：US17730881

申请日：2022-04-27

Applicant: Socionext Inc.

Inventor： Masahisa Iida ,  Toshihiro Nakamura

IPC: H10D84/90 ,  H03K19/177

Abstract: An IO cell includes a first output transistor and a second output transistor. A capacitance transistor is provided between external connection pads. The capacitance transistor is placed between the output transistors and an edge of the semiconductor integrated circuit device as viewed in plan. The gate length of the capacitance transistor is smaller than the gate length of the output transistors.

公开(公告)号：US11621705B2

公开(公告)日：2023-04-04

申请号：US17122737

申请日：2020-12-15

Applicant: SOCIONEXT INC.

Inventor： Masahisa Iida ,  Masahiro Gion

IPC: H03K3/356 ,  H03K19/003 ,  H03K19/0185

Abstract: A semiconductor integrated circuit device includes: first and second transistors provided between a first power source and an output terminal; a step-down circuit that generates a second power source from the first power source; a power source switch circuit that outputs, as a fourth power source, a higher one of potentials of the second power source and a third power source; and a level shifter circuit that transits between the first power source and a fourth power source. The first transistor has a gate connected to an output of the level shifter circuit; the second transistor has a gate connected to the fourth power source.

公开(公告)号：US20190386653A1

公开(公告)日：2019-12-19

申请号：US16557851

申请日：2019-08-30

Applicant: Socionext Inc.

Inventor： Masahisa Iida

IPC: H03K17/16

Abstract: A semiconductor integrated circuit includes: a power supply terminal that receives a power supply voltage; an external terminal; an output PMOS transistor connected between the power supply terminal and the external terminal; an auxiliary PMOS transistor connected between a gate of the output PMOS transistor and the external terminal; and a bias voltage generating circuit connected to a gate of the auxiliary PMOS transistor. The bias voltage generating circuit supplies a voltage lower than the power supply voltage to the gate of the auxiliary PMOS transistor, if it is necessary to maintain an OFF state of the output PMOS transistor by supplying an external voltage received at the external terminal to the gate of the output PMOS transistor.

公开(公告)号：US10439596B2

公开(公告)日：2019-10-08

申请号：US16160238

申请日：2018-10-15

Applicant: SOCIONEXT INC.

Inventor： Masahisa Iida

IPC: H03K3/00 ,  H03K3/012 ,  H03K17/687 ,  H03K19/0185 ,  H03K19/20

Abstract: In order to reduce a signal propagation delay when an input signal falls, an NMOS transistor (M1) is connected between an input terminal (1) receiving a signal having an amplitude of 3.3 V and an input of an inverter (INV1). A first PMOS transistor (M2) having a low drive capability and a second PMOS transistor (M4) having a high drive capability are connected in parallel between a power supply terminal (VDD 18) supplying 1.8 V and a gate of the NMOS transistor (M1). A gate of the first PMOS transistor (M2) is connected to the input of the inverter (INV1). A gate of the second PMOS transistor (M4) is connected to an output of the inverter (INV1).

公开(公告)号：US10763849B2

公开(公告)日：2020-09-01

申请号：US16557851

申请日：2019-08-30

Applicant: Socionext Inc.

Inventor： Masahisa Iida

IPC: H03K17/16

Abstract: A semiconductor integrated circuit includes: a power supply terminal that receives a power supply voltage; an external terminal; an output PMOS transistor connected between the power supply terminal and the external terminal; an auxiliary PMOS transistor connected between a gate of the output PMOS transistor and the external terminal; and a bias voltage generating circuit connected to a gate of the auxiliary PMOS transistor. The bias voltage generating circuit supplies a voltage lower than the power supply voltage to the gate of the auxiliary PMOS transistor, if it is necessary to maintain an OFF state of the output PMOS transistor by supplying an external voltage received at the external terminal to the gate of the output PMOS transistor.

公开(公告)号：US10355685B2

公开(公告)日：2019-07-16

申请号：US16001199

申请日：2018-06-06

Applicant: SOCIONEXT INC.

Inventor： Masahisa Iida ,  Masahiro Gion

IPC: H03K17/04 ,  H03K17/687 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0944 ,  H03K19/0185

Abstract: An output transistor (2) has a source connected to a VDD1 and a drain connected to an output terminal (1). A pre-driver (3) receives a signal varying in accordance with a data input signal (DIN), and provides a gate signal (SG1) to a gate of the output transistor (2), the gate signal (SG1) transiting between the VDD1 and a potential (VP) at a power source end (4). When a VDD2 is output from an output node (N1) and an assist signal (SA) makes a first transition corresponding to the transition of the gate signal (SG1) from HIGH to LOW, the drive assist circuit (20) performs an assist operation in which a potential of the output node (N1) is temporarily brought down from VDD2.