公开(公告)号：US11025237B1

公开(公告)日：2021-06-01

申请号：US16827985

申请日：2020-03-24

Applicant: SiFive, Inc.

Inventor： Santosh Mahadeo Narawade ,  Jithin K ,  Mohit Gupta

IPC: H03K19/0175 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/003 ,  H03K19/017 ,  H03K19/00

Abstract: Described is a high speed, low power level shifter circuit which includes a level shifter coupled to a sensing circuit. The level shifter includes a pair of source transistors, a pair of input transistors, and a pair of switching circuits connected between the source transistors and the input transistors. The sensing circuit turns off a switching circuit on an active side of the level shifter based on detecting that an output voltage of the level shifter has completed a voltage level transition from a first logic level voltage to a second logic level voltage. An open circuit is established on the active side and turns off the pair of source transistors. The other switching circuit is turned on. Static current flow on the active side of the level shifter is stopped and the output voltage is latched to a voltage representative of the second logic level voltage.

公开(公告)号：US10965278B1

公开(公告)日：2021-03-30

申请号：US16827963

申请日：2020-03-24

Applicant: SiFive, Inc.

Inventor： Santosh Mahadeo Narawade ,  Jithin K ,  Mohit Gupta

IPC: H03K3/356 ,  H03K19/0185

Abstract: Described is a high speed, low power level shifter circuit which includes a cross-coupled level shifter coupled to a sensing circuit. The sensing circuit turns off a cross-coupled node of a pair of cross-coupled nodes based on detecting that an input voltage has crossed a threshold voltage for a cross-coupled input transistor of a pair of cross-coupled input transistors, i.e. due to switching from a current logic level to an incoming logic level. Once the sensing circuit detects a threshold voltage crossing, a pull-up circuit pulls high a cross-coupled node and cross-coupled source transistor tied to the cross-coupled node. This turns off the cross-coupled source transistor and turns on another cross-coupled source transistor. Two parallel paths are now established to pull the cross-coupled node high, enabling a high-speed transition. The turning off of the cross-coupled source transistor also pulls the output to the incoming logic level.

公开(公告)号：US20220200586A1

公开(公告)日：2022-06-23

申请号：US17690583

申请日：2022-03-09

Applicant: SiFive, Inc.

Inventor： Santosh Mahadeo Narawade ,  Jithin K ,  Mohit Gupta

IPC: H03K3/3565 ,  H03K3/356

Abstract: Systems and methods are disclosed for low-swing Schmitt triggers. For example, an apparatus includes a Schmitt trigger including an input node, an output node, and a feedback node that is configured to bear a feedback voltage level that is a sum of an input voltage level at the input node and an attenuated voltage level of the output node; a current source connected to the output node; a voltage sensor connected to the feedback node and configured to cause the current source to pull up an output voltage level at the output node responsive to the feedback voltage level crossing a threshold.

公开(公告)号：US11296683B2

公开(公告)日：2022-04-05

申请号：US16827989

申请日：2020-03-24

Applicant: SiFive, Inc.

Inventor： Santosh Mahadeo Narawade ,  Jithin K ,  Mohit Gupta

IPC: H03K3/3565 ,  H03K3/356

Abstract: Systems and methods are disclosed for low-swing Schmitt triggers. For example, an apparatus includes a Schmitt trigger including an input node, an output node, and a feedback node that is configured to bear a feedback voltage level that is a sum of an input voltage level at the input node and an attenuated voltage level of the output node; a current source connected to the output node; a voltage sensor connected to the feedback node and configured to cause the current source to pull up an output voltage level at the output node responsive to the feedback voltage level crossing a threshold.

公开(公告)号：US20210305972A1

公开(公告)日：2021-09-30

申请号：US16827989

申请日：2020-03-24

Applicant: SiFive, Inc.

Inventor： Santosh Mahadeo Narawade ,  Jithin K ,  Mohit Gupta

IPC: H03K3/3565 ,  H03K3/356

Abstract: Systems and methods are disclosed for low-swing Schmitt triggers. For example, an apparatus includes a Schmitt trigger including an input node, an output node, and a feedback node that is configured to bear a feedback voltage level that is a sum of an input voltage level at the input node and an attenuated voltage level of the output node; a current source connected to the output node; a voltage sensor connected to the feedback node and configured to cause the current source to pull up an output voltage level at the output node responsive to the feedback voltage level crossing a threshold.

公开(公告)号：US11063597B1

公开(公告)日：2021-07-13

申请号：US16827969

申请日：2020-03-24

Applicant: SiFive, Inc.

Inventor： Santosh Mahadeo Narawade ,  Jithin K ,  Mohit Gupta

IPC: H03L7/081 ,  H03L7/085 ,  H03K5/134 ,  H03L7/07

Abstract: Described is a delay-locked loop which includes a frontend circuit configured to output a control voltage based on an input clock and a feedback clock and a delay line circuit connected to the frontend circuit. The delay line circuit configured to generate a bias voltage based on the control voltage and a step size, where the bias voltage is variable based on the step size, and apply at least one level of delay on the input clock based on the bias voltage to generate an output clock, where the feedback clock being based on the output clock and where the input clock is aligned with the feedback clock by delaying the phase of the output clock until phase lock.