公开(公告)号：US12002820B2

公开(公告)日：2024-06-04

申请号：US17591042

申请日：2022-02-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Jun Nishimura ,  Akira Tagawa ,  Yohei Takeuchi ,  Yasuaki Iwase

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1251 ,  H01L27/124 ,  H01L29/78633 ,  H01L27/1225

Abstract: An active matrix substrate includes first and second TFTs. The first TFT includes a first lower electrode, a first insulating layer, a first oxide semiconductor layer, and a first gate electrode. The first oxide semiconductor layer includes a first channel region overlapping the first gate electrode when viewed in a normal direction of the substrate. The first lower electrode has a first light-shielding portion overlapping the entire first channel region and including a first metal film. The second TFT includes a second lower electrode, the first insulating layer, a second oxide semiconductor layer, and a second gate electrode. The second oxide semiconductor layer includes a second channel region overlapping the second gate electrode when viewed in the normal direction. The second lower electrode has a light-transmitting portion overlapping the second channel region and including a first transparent conductive film but not a light-shielding metal film.

公开(公告)号：US10984747B2

公开(公告)日：2021-04-20

申请号：US16935238

申请日：2020-07-22

Applicant: Sharp Kabushiki Kaisha

Inventor： Akira Tagawa ,  Takuya Watanabe ,  Jun Nishimura ,  Yasuaki Iwase ,  Yohei Takeuchi

IPC: G09G3/36

Abstract: In a display device including an active matrix substrate in which a demultiplexing circuit is formed, a boost circuit, which generates a plurality of connection control signals respectively applied to gate terminals of a plurality of connection control transistors as switching elements configuring the demultiplexing circuit are respectively generated, is provided in the demultiplexing circuit. An internal node of each boost circuit is precharged via a transistor turned on by a boosted voltage of an internal node of another boost circuit, and thereafter, a voltage of the internal node of the boost circuit is boosted via a boost capacitor by a control signal applied to a demultiplexing circuit. The boosted voltage of the internal node is applied to a gate terminal of a connection control transistor as a connection control signal.

公开(公告)号：US10923064B2

公开(公告)日：2021-02-16

申请号：US16500427

申请日：2018-04-10

Applicant: Sharp Kabushiki Kaisha

Inventor： Yohei Takeuchi ,  Takuya Watanabe ,  Yasuaki Iwase ,  Akira Tagawa

IPC: G09G3/36 ,  G11C19/18 ,  G11C19/28

Abstract: A gate driver (scanning signal line drive circuit) that can allow a gate output to promptly fall without causing a deterioration in a transistor is implemented. A gate-output fall transistor (T01) and a gate-output stabilization transistor (T02) are provided near an output portion of the unit circuit that constitutes a shift register. A first gate low voltage (Vgl1) having a voltage level that is conventionally used to bring pixel TFTs into an off state is provided to a source terminal of the gate-output stabilization transistor (T02), and a second gate low voltage (Vgl2) having a lower voltage level than the first gate low voltage (Vgl1) is provided to a source terminal of the gate-output fall transistor (T01). Upon allowing the gate output to fall, the gate-output fall transistor (T01) is brought into an on state and then the gate-output stabilization transistor (T02) is brought into an on state.

公开(公告)号：US11328682B2

公开(公告)日：2022-05-10

申请号：US17226864

申请日：2021-04-09

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Yasuaki Iwase ,  Takuya Watanabe ,  Akira Tagawa ,  Jun Nishimura ,  Yohei Takeuchi

IPC: G09G3/36 ,  G11C19/28

Abstract: A gate driver is constituted of a first gate driver including a first shift register that is configured by bistable circuits corresponding to gate bus lines on odd-numbered lines arranged on one side of a display portion, and a second gate driver including a second shift register that is configured by bistable circuits corresponding to gate bus lines on even-numbered lines arranged on another side of the display portion. A first buffer circuit is provided on one end side of each gate bus line, and a second buffer circuit is provided on another end side of each gate bus line. A control signal for controlling the scanning order of the gate bus line is given to the bistable circuit and the second buffer circuit.

公开(公告)号：US11100882B1

公开(公告)日：2021-08-24

申请号：US17134926

申请日：2020-12-28

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Yohei Takeuchi ,  Akira Tagawa ,  Yasuaki Iwase ,  Jun Nishimura

IPC: G09G3/36

Abstract: In a display device that adopts an SSD scheme, a demultiplexer circuit has provided for each source bus line, a compensating transistor whose first conduction terminal is connected to the source bus line and whose second conducting terminal is maintained in a floating state. In such a configuration, for example, at the same timing as a connection control transistor changes from an on state to an off state due to a change from a high level to a low level of a control signal that is supplied to a control terminal of the connection control transistor, a control signal that is supplied to a control terminal of the compensating transistor changes from the low level to the high level.

公开(公告)号：US10984744B2

公开(公告)日：2021-04-20

申请号：US16579895

申请日：2019-09-24

Applicant: Sharp Kabushiki Kaisha

Inventor： Yohei Takeuchi ,  Takuya Watanabe ,  Akira Tagawa ,  Yasuaki Iwase ,  Jun Nishimura

IPC: G06F3/038 ,  G09G5/00 ,  G09G3/36

Abstract: To prevent a decrease in display quality caused when a display apparatus performs pause driving. One end of the n-th scanning signal line (GLn) is connected to the n-th stage circuit (UCn) of a driver circuit. The other end of the n-th scanning signal line is connected to a waveform adjusting circuit (HKn) which adjusts the waveform of the pulse signal of the n-th scanning signal line (GLn) by using a clock signal (CKA) and the pulse signal of the m-th scanning signal line (GLn−1) scanned prior to the n-th scanning signal line.

公开(公告)号：US10796659B2

公开(公告)日：2020-10-06

申请号：US16390033

申请日：2019-04-22

Applicant: Sharp Kabushiki Kaisha

Inventor： Akira Tagawa ,  Yasuaki Iwase ,  Takuya Watanabe ,  Takatsugu Kusumi ,  Yohei Takeuchi

IPC: G09G3/36 ,  G11C19/28

Abstract: There is adopted a gate driver with a system of applying a direct current voltage as an active scanning signal to a gate bus line through a buffer transistor in a unit circuit that composes a shift register, and a display device is provided with a direct current voltage generation circuit that generates the direct current voltage. The direct current voltage generation circuit changes a voltage level of the direct current voltage in each frame period. For example, when a direct current voltage input terminal is provided on a vertical scanning end side, the direct current voltage generation circuit gradually decreases the voltage level of the direct current voltage in each frame period.

公开(公告)号：US10902813B2

公开(公告)日：2021-01-26

申请号：US16191234

申请日：2018-11-14

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Yohei Takeuchi ,  Takuya Watanabe ,  Akira Tagawa ,  Yasuaki Iwase ,  Takatsugu Kusumi

IPC: G11C19/00 ,  G09G3/36 ,  G11C19/28 ,  G06F3/041

Abstract: Each unit circuit that constitutes each of stages of a shift register is provided with a charge supply unit including a third node whose potential becomes high level at identical timing with a first node (a node for holding an electric charge in order to output a scanning signal (output signal) at high level), and capable of supplying an electric charge to the first node throughout a period after the potential of the third node becomes high level until the scanning signal (output signal) at high level is outputted. Here, all of the unit circuits within the shift register have an identical configuration.

公开(公告)号：US10818260B2

公开(公告)日：2020-10-27

申请号：US16191226

申请日：2018-11-14

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Akira Tagawa ,  Takuya Watanabe ,  Yasuaki Iwase ,  Takatsugu Kusumi ,  Yohei Takeuchi

IPC: G09G3/36 ,  G11C19/28 ,  G06F3/041

Abstract: Each unit circuit includes a thin film transistor (first stabilization transistor) having a gate terminal to which a clear signal which goes to an on level when a frame period ends applied, a drain terminal connected to a charge holding node, and a source terminal to which a potential of an off level is applied. Here, a gate length of the thin film transistor is set to be larger than gate lengths of other charge holding node turn-off transistors. Alternatively, a multi-gate structure is adopted for the thin film transistor and a single gate structure is adopted for the other charge holding node turn-off transistors.

公开(公告)号：US10796655B2

公开(公告)日：2020-10-06

申请号：US16234347

申请日：2018-12-27

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Takatsugu Kusumi ,  Takuya Watanabe ,  Akira Tagawa ,  Yasuaki Iwase ,  Yohei Takeuchi

IPC: G09G3/36 ,  G02F1/1368 ,  H01L27/12

Abstract: A configuration in which a voltage (a gate on voltage) of only one system is used as a voltage for turning scanning lines to a selected state is employed (single power supply system configuration). A unit circuit that constitutes a shift register within a gate driver includes a thin film transistor whose source terminal is connected to an output control node. In such a configuration, when the external power supply is stopped, a voltage supplied to a gate terminal of the thin film transistor and a voltage supplied to a drain terminal of the thin film transistor are set to the gate on voltage.