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公开(公告)号：US20200351577A1
公开(公告)日：2020-11-05
申请号：US16401107
申请日：2019-05-01
Applicant: Semtech Corporation
Inventor： Miguel Valencia , Nirmal Bissonauth
IPC: H04Q11/00 , H04B10/077
Abstract: A signal detection circuit has a first differential amplifier including a first input coupled for receiving a data signal, and a second input coupled for receiving a threshold signal. A current steering circuit is coupled to an output of the first differential amplifier to establish a threshold for the first differential amplifier. A latch has an input coupled to the output of the first differential amplifier for latching a signal detect. A second amplifier has an input coupled to the output of the first differential amplifier and an output coupled to the input of the latch. A third amplifier has an input coupled to the output of the first differential amplifier and an output providing the data signal. The current steering circuit can be disabled which removes the need for the third amplifier as the data signal path is through second amplifier.
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公开(公告)号：US10972815B2
公开(公告)日：2021-04-06
申请号：US16401107
申请日：2019-05-01
Applicant: Semtech Corporation
Inventor： Miguel Valencia , Nirmal Bissonauth
IPC: H04Q11/00 , H04B10/077
Abstract: A signal detection circuit has a first differential amplifier including a first input coupled for receiving a data signal, and a second input coupled for receiving a threshold signal. A current steering circuit is coupled to an output of the first differential amplifier to establish a threshold for the first differential amplifier. A latch has an input coupled to the output of the first differential amplifier for latching a signal detect. A second amplifier has an input coupled to the output of the first differential amplifier and an output coupled to the input of the latch. A third amplifier has an input coupled to the output of the first differential amplifier and an output providing the data signal. The current steering circuit can be disabled which removes the need for the third amplifier as the data signal path is through second amplifier.
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Patent Agency Ranking
公开(公告)号：US10892745B2
公开(公告)日：2021-01-12
申请号：US16374489
申请日：2019-04-03
Applicant: Semtech Corporation
Inventor： Miguel Valencia , Guang Yang
Abstract: A circuit detects a digital pattern with a first counter having an input receiving a digital pattern, and an output providing an output signal after detecting a first number of pulses during a first time period. A latch has an input coupled to the output of the first counter for latching the output signal of the first counter. A second counter has an input receiving the digital pattern, and an output providing an output signal after detecting a second number of pulses during a second time period. A logic gate has a first input coupled the output of the first counter, and a second input coupled to the output of the second counter, and an output coupled to the input of the latch. An amplitude detection circuit has an input coupled for receiving the digital pattern and an output coupled to the input of the first counter.
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公开(公告)号：US10862466B2
公开(公告)日：2020-12-08
申请号：US16271824
申请日：2019-02-09
Applicant: Semtech Corporation
Inventor： Miguel Valencia , Nikolaos Vogiatzis
Abstract: A circuit controls a dynamic time constant to remove DC offset from a received optical data signal. The circuit has a first capacitor coupled between a first terminal and a second terminal. A first resistance network is coupled between the second terminal and a reference voltage. A control circuit has a first output coupled to a control input of the first resistance network. The control circuit monotonically increases an effective resistance of the first resistance network to increase the dynamic time constant. The first resistance network has a resistor coupled to the second terminal, and a transistor with a first conduction terminal coupled to the resistor, a second conduction terminal coupled to the reference voltage, and a control terminal coupled to the first output of the control circuit. The first capacitor has a variable capacitance. The monotonic increase in the dynamic time constant can be linear or non-linear.
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公开(公告)号：US20200259485A1
公开(公告)日：2020-08-13
申请号：US16271824
申请日：2019-02-09
Applicant: Semtech Corporation
Inventor： Miguel Valencia , Nikolaos Vogiatzis
Abstract: A circuit controls a dynamic time constant to remove DC offset from a received optical data signal. The circuit has a first capacitor coupled between a first terminal and a second terminal. A first resistance network is coupled between the second terminal and a reference voltage. A control circuit has a first output coupled to a control input of the first resistance network. The control circuit monotonically increases an effective resistance of the first resistance network to increase the dynamic time constant. The first resistance network has a resistor coupled to the second terminal, and a transistor with a first conduction terminal coupled to the resistor, a second conduction terminal coupled to the reference voltage, and a control terminal coupled to the first output of the control circuit. The first capacitor has a variable capacitance. The monotonic increase in the dynamic time constant can be linear or non-linear.
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公开(公告)号：US20200321951A1
公开(公告)日：2020-10-08
申请号：US16374489
申请日：2019-04-03
Applicant: Semtech Corporation
Inventor： Miguel Valencia , Guang Yang
Abstract: A circuit detects a digital pattern with a first counter having an input receiving a digital pattern, and an output providing an output signal after detecting a first number of pulses during a first time period. A latch has an input coupled to the output of the first counter for latching the output signal of the first counter. A second counter has an input receiving the digital pattern, and an output providing an output signal after detecting a second number of pulses during a second time period. A logic gate has a first input coupled the output of the first counter, and a second input coupled to the output of the second counter, and an output coupled to the input of the latch. An amplitude detection circuit has an input coupled for receiving the digital pattern and an output coupled to the input of the first counter.
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公开(公告)号：US10345837B1
公开(公告)日：2019-07-09
申请号：US15958967
申请日：2018-04-20
Applicant: Semtech Corporation
Inventor： Miguel Valencia
Abstract: A voltage regulator has a comparator and a reference voltage coupled to a first input of the comparator. An output voltage of the voltage regulator is coupled to a second input of the comparator through a resistor. A current source is coupled to the second input of the comparator. The first current source can be a first digital-to-analog converter (DAC). A second current source can be coupled in parallel with the first DAC. The second current source can be a second DAC. The voltage regulator can include a boost topology.
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