公开(公告)号：US10776601B2

公开(公告)日：2020-09-15

申请号：US16027620

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woonbae Kim ,  Jikho Song ,  Sungeun Jo ,  Ji-Yong Park ,  Jeong-Kyu Ha

IPC: G06K9/28 ,  G06K9/00 ,  G09G3/3208

Abstract: Disclosed are fingerprint sensor packages and display apparatuses including the same. The fingerprint sensor package comprises a flexible film having a top surface and a bottom surface opposite to the top surface, a fingerprint sensor surrounded by a cap, and a display driver integrated circuit on the flexible film. The fingerprint sensor and the display driver integrated circuit are mounted on the top surface of the flexible film.

公开(公告)号：US09589842B2

公开(公告)日：2017-03-07

申请号：US14993054

申请日：2016-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho Choi ,  Donghan Kim ,  Jae Choon Kim ,  Jikho Song ,  Mitsuo Umemoto

IPC: H01L21/44 ,  H01L23/485 ,  H01L21/78 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/3511

Abstract: A method of fabricating a semiconductor package is disclosed. The method includes disposing semiconductor chips on a support substrate, forming a protection layer covering top surfaces of the semiconductor chips, forming a molding layer covering the support substrate and the protection layer, and etching the molding layer to expose the protection layer.

Abstract translation: 公开了制造半导体封装的方法。 该方法包括将半导体芯片布置在支撑基板上，形成覆盖半导体芯片顶表面的保护层，形成覆盖支撑基板和保护层的模制层，以及蚀刻模塑层以露出保护层。

公开(公告)号：US20160197057A1

公开(公告)日：2016-07-07

申请号：US14955516

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mitsuo Umemoto ,  Donghan Kim ,  Jae Choon Kim ,  Jikho Song ,  Inho Choi

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3192 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The invention relates to a semiconductor package that includes a connection member disposed at one side of the semiconductor chip, an insulating layer covering bottom surfaces of the semiconductor chip and the connection member, a molding layer that is disposed on the insulating layer and covers a side surface of the semiconductor chip and a top surface and opposing side surfaces of the connection member, an electric line disposed on the insulating layer and electrically connected to the semiconductor chip and the connection member, and an external terminal disposed on the insulating layer and electrically connected to the electric line.

Abstract translation: 本发明涉及一种半导体封装，其包括设置在半导体芯片的一侧的连接构件，覆盖半导体芯片的底面和连接构件的绝缘层，模制层，其设置在绝缘层上并覆盖一侧 半导体芯片的表面和连接构件的顶表面和相对的侧表面，设置在绝缘层上并电连接到半导体芯片和连接构件的电线以及设置在绝缘层上并电连接的外部端子 到电线。