公开(公告)号：US09673093B2

公开(公告)日：2017-06-06

申请号：US14449914

申请日：2014-08-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Ming-Che Hsieh ,  Chien Chen Lee ,  Baw-Ching Perng

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/525 ,  H01L23/532 ,  H01L21/56 ,  H01L23/14 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49894 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/0001 ,  H01L2924/01007 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/207 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

公开(公告)号：US20150041985A1

公开(公告)日：2015-02-12

申请号：US14449914

申请日：2014-08-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Ming-Che Hsieh ,  Chien Chen Lee ,  Baw-Ching Perng

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49894 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/0001 ,  H01L2924/01007 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/207 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

Abstract translation: 半导体器件具有半导体晶片和形成在半导体晶片上的第一导电层作为接触焊盘。 形成在第一导电层上的第一绝缘层。 在第一导电层和第一绝缘层上形成包括互连部位的第二导电层。 第二导电层形成为再分布层。 第二绝缘层形成在第二导电层上。 在互连部位上的第二绝缘层中形成开口。 开口延伸到与互连部位相邻的区域中的第一绝缘层。 或者，开口在与互连部位相邻的区域中部分延伸穿过第二绝缘层。 互连结构形成在互连位置的开口内并且在第二导电层的侧表面上。 将半导体晶片分成单独的半导体晶片。

公开(公告)号：US20140319695A1

公开(公告)日：2014-10-30

申请号：US14223695

申请日：2014-03-24

Applicant: STATS ChipPAC, Ltd.

Inventor： Ming-Che Hsieh ,  Chien Chen Lee

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/02145 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/0665

Abstract: A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A first insulating layer is formed over the substrate. A second insulating layer is formed over the first insulating layer. A second conductive layer is formed over the second insulating layer. The second insulating layer is formed to include a cylindrical shape. The second conductive layer is formed as an under bump metallization layer. A first opening is formed in the second insulating layer. A second opening is formed in the second insulating layer around the first opening in the second insulating layer. An opening is formed in the first insulating layer over the first conductive layer. An opening is formed in the second insulating layer over the first conductive layer with the opening of the first insulating layer being greater than the opening of the second insulating layer.

Abstract translation: 半导体器件具有基板。 第一导电层形成在衬底上。 在衬底上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 在第二绝缘层上形成第二导电层。 第二绝缘层形成为包括圆筒形状。 第二导电层形成为凸块下金属化层。 在第二绝缘层中形成第一开口。 在第二绝缘层中的第二绝缘层中的第一开口周围形成有第二开口。 在第一导电层上的第一绝缘层中形成开口。 在所述第一导电层上的所述第二绝缘层中形成开口，所述第一绝缘层的开口大于所述第二绝缘层的开口。

公开(公告)号：US09349700B2

公开(公告)日：2016-05-24

申请号：US14223695

申请日：2014-03-24

Applicant: STATS ChipPAC, Ltd.

Inventor： Ming-Che Hsieh ,  Chien Chen Lee

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/02145 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/35 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/0665

Abstract: A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A first insulating layer is formed over the substrate. A second insulating layer is formed over the first insulating layer. A second conductive layer is formed over the second insulating layer. The second insulating layer is formed to include a cylindrical shape. The second conductive layer is formed as an under bump metallization layer. A first opening is formed in the second insulating layer. A second opening is formed in the second insulating layer around the first opening in the second insulating layer. An opening is formed in the first insulating layer over the first conductive layer. An opening is formed in the second insulating layer over the first conductive layer with the opening of the first insulating layer being greater than the opening of the second insulating layer.

Abstract translation: 半导体器件具有基板。 第一导电层形成在衬底上。 在衬底上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 在第二绝缘层上形成第二导电层。 第二绝缘层形成为包括圆筒形状。 第二导电层形成为凸块下金属化层。 在第二绝缘层中形成第一开口。 在第二绝缘层中的第二绝缘层中的第一开口周围形成有第二开口。 在第一导电层上的第一绝缘层中形成开口。 在所述第一导电层上的所述第二绝缘层中形成开口，所述第一绝缘层的开口大于所述第二绝缘层的开口。

公开(公告)号：US20140225256A1

公开(公告)日：2014-08-14

申请号：US14256047

申请日：2014-04-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Jen Yu Chen ,  Ting Yu Fu ,  Men Hsien Li ,  Chien Chen Lee

IPC: H01L23/00

CPC classification number: H01L24/10 ,  H01L22/12 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11903 ,  H01L2224/13 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16058 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor die and conductive pillar with a recess or protrusion formed over a surface of the semiconductor die. The conductive pillar is made by forming a patterning layer over the semiconductor die, forming an opening with a recess or protrusion in the patterning layer, depositing conductive material in the opening and recess or protrusion, and removing the patterning layer. A substrate has bump material deposited over a conductive layer formed over a surface of the substrate. The bump material is melted. The semiconductor die is pressed toward the substrate to enable the melted bump material to flow into the recess or over the protrusion if the conductive pillar makes connection to the conductive layer. A presence or absence of the bump material in the recess or protrusion of the conductive pillar is detected by X-ray or visual inspection.

Abstract translation: 半导体器件具有在半导体管芯的表面上形成的具有凹部或突起的半导体管芯和导电柱。 导电柱通过在半导体管芯上形成图案化层而形成，在图案化层中形成具有凹部或突起的开口，在开口和凹部或突起中沉积导电材料，并除去图案形成层。 衬底具有沉积在形成在衬底的表面上的导电层上的凸起材料。 凸块材料熔化。 如果导电柱与导电层连接，则将半导体管芯压向衬底，以使熔融的凸块材料流入凹槽或突出部上。 通过X射线或视觉检查来检测导电柱的凹部或突起中是否存在凸块材料。

公开(公告)号：US09478513B2

公开(公告)日：2016-10-25

申请号：US14256047

申请日：2014-04-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Jen Yu Chen ,  Ting Yu Fu ,  Men Hsien Li ,  Chien Chen Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/66

CPC classification number: H01L24/10 ,  H01L22/12 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11903 ,  H01L2224/13 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16058 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor die and conductive pillar with a recess or protrusion formed over a surface of the semiconductor die. The conductive pillar is made by forming a patterning layer over the semiconductor die, forming an opening with a recess or protrusion in the patterning layer, depositing conductive material in the opening and recess or protrusion, and removing the patterning layer. A substrate has bump material deposited over a conductive layer formed over a surface of the substrate. The bump material is melted. The semiconductor die is pressed toward the substrate to enable the melted bump material to flow into the recess or over the protrusion if the conductive pillar makes connection to the conductive layer. A presence or absence of the bump material in the recess or protrusion of the conductive pillar is detected by X-ray or visual inspection.

Abstract translation: 半导体器件具有在半导体管芯的表面上形成的具有凹部或突起的半导体管芯和导电柱。 导电柱通过在半导体管芯上形成图案化层而形成，在图案化层中形成具有凹部或突起的开口，在开口和凹部或突起中沉积导电材料，并除去图案形成层。 衬底具有沉积在形成在衬底的表面上的导电层上的凸起材料。 凸块材料熔化。 如果导电柱与导电层连接，则将半导体管芯压向衬底，以使熔融的凸块材料流入凹槽或突出部上。 通过X射线或视觉检查来检测导电柱的凹部或突起中是否存在凸块材料。