公开(公告)号：US11004956B2

公开(公告)日：2021-05-11

申请号：US16685941

申请日：2019-11-15

Applicant: SK hynix Inc.

Inventor： Jin Ha Kim

IPC: H01L29/66 ,  H01L21/02 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/112 ,  H01L27/24 ,  H01L21/306

Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure, forming an opening in the stacked structure, forming a preliminary channel layer in the opening, forming a channel layer by performing heat treatment on the preliminary channel layer, etching an inner surface of the channel layer, and performing ozone (O3) treatment on an etched inner surface of the channel layer.

公开(公告)号：US09257487B2

公开(公告)日：2016-02-09

申请号：US14856125

申请日：2015-09-16

Applicant: SK hynix Inc.

Inventor： Isaac Chung ,  Jin Ha Kim

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/115 ,  H01L27/24 ,  H01L45/00 ,  H01L29/423 ,  H01L23/48 ,  H01L27/105

CPC classification number: H01L27/2481 ,  H01L21/76802 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/481 ,  H01L27/088 ,  H01L27/1052 ,  H01L27/2436 ,  H01L27/2454 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.

公开(公告)号：US11974436B2

公开(公告)日：2024-04-30

申请号：US18082326

申请日：2022-12-15

Applicant: SK hynix Inc.

Inventor： Jin Ha Kim

IPC: H10B43/27 ,  H10B41/27 ,  H10B63/00

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B63/845

Abstract: A semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked with each other, and a channel layer passing through the stacked structure, wherein the channel layer is a single layer, the single layer including a first GIDL region, a cell region, and a second GIDL region, and the first GIDL region has a greater thickness than each of the cell region and the second GIDL region.

公开(公告)号：US09935194B2

公开(公告)日：2018-04-03

申请号：US15370922

申请日：2016-12-06

Applicant: SK hynix Inc.

Inventor： Jin Ha Kim ,  Jun Kwan Kim ,  Kang Sik Choi ,  Su Jin Chae ,  Young Ho Lee

IPC: H01L29/94 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/28 ,  H01L27/24 ,  H01L29/45 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L29/7827 ,  H01L21/28518 ,  H01L21/28531 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/2454 ,  H01L29/456

Abstract: A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.

公开(公告)号：US09905567B2

公开(公告)日：2018-02-27

申请号：US15295042

申请日：2016-10-17

Applicant: SK hynix Inc.

Inventor： Jin Ha Kim

IPC: H01L29/76 ,  H01L31/036 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/423 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/04

CPC classification number: H01L27/11568 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/792 ,  H01L29/7926

Abstract: A semiconductor integrated circuit device may include a structure, a first capping layer, a channel layer and a second capping layer. The structure may have an opening formed in the structure. The first capping layer may be formed in the opening of the structure. The channel layer may be arranged between the structure and the first capping layer. The second capping layer may be arranged on the channel layer and the first capping layer.

公开(公告)号：US09240479B1

公开(公告)日：2016-01-19

申请号：US14856082

申请日：2015-09-16

Applicant: SK hynix Inc.

Inventor： Isaac Chung ,  Jin Ha Kim

IPC: H01L21/8247 ,  H01L23/528 ,  H01L29/78 ,  H01L27/24 ,  H01L29/423 ,  H01L27/088 ,  H01L21/768 ,  H01L23/48 ,  H01L27/105

CPC classification number: H01L27/2481 ,  H01L21/76802 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/481 ,  H01L27/088 ,  H01L27/1052 ,  H01L27/2436 ,  H01L27/2454 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.

公开(公告)号：US12243818B2

公开(公告)日：2025-03-04

申请号：US17552944

申请日：2021-12-16

Applicant: SK hynix Inc.

Inventor： Jin Ha Kim

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: A memory device, and a method of manufacturing the same, includes interlayer insulation layers spaced apart from each other and stacked, gate lines formed between the interlayer insulation layers, and a plug vertically passing through the interlayer insulation layers and the gate lines. Each of the gate lines includes a barrier layer formed along an inner wall of the interlayer insulation layer and the plug, a first conductive layer surrounded by the barrier layer, and a second conductive layer surrounded by the first conductive layer. A material of the second conductive layer is different from a material of the first conductive layer, and a size of the second conductive layer is variable along a direction in which the gate lines extend.

公开(公告)号：US11600714B2

公开(公告)日：2023-03-07

申请号：US17229617

申请日：2021-04-13

Applicant: SK hynix Inc.

Inventor： Jin Ha Kim

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/112 ,  H01L27/24

Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure, forming an opening in the stacked structure, forming a preliminary channel layer in the opening, forming a channel layer by performing heat treatment on the preliminary channel layer, etching an inner surface of the channel layer, and performing ozone (O3) treatment on an etched inner surface of the channel layer.

公开(公告)号：US11522052B2

公开(公告)日：2022-12-06

申请号：US16917666

申请日：2020-06-30

Applicant: SK hynix Inc.

Inventor： Jin Ha Kim

IPC: H01L27/11568 ,  H01L29/10 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/24 ,  H01L25/18

Abstract: A semiconductor device includes a stack including alternately stacked conductive films and insulating films, wherein the stack includes an opening penetrating the conductive films and the insulating films, and wherein the stack includes a rounded corner that is exposed to the opening. The semiconductor device also includes a first channel film formed in the opening and including a first curved surface surrounding the rounded corner. The semiconductor device further includes a conductive pad formed in the opening, and a second channel film interposed between the first curved surface of the first channel film and the conductive pad.

公开(公告)号：US11114457B2

公开(公告)日：2021-09-07

申请号：US16659889

申请日：2019-10-22

Applicant: SK hynix Inc.

Inventor： Jin Ha Kim

IPC: H01L27/11582 ,  H01L27/24 ,  H01L27/11556

Abstract: A semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked with each other, and a channel layer passing through the stacked structure, wherein the channel layer is a single layer, the single layer including a first GIDL region, a cell region, and a second GIDL region, and the first GIDL region has a greater thickness than each of the cell region and the second GIDL region.