公开(公告)号：US09613881B2

公开(公告)日：2017-04-04

申请号：US14891629

申请日：2014-05-09

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Heui Gyun Ahn ,  Sang Wook Ahn ,  Yong Woon Lee ,  Huy Chan Jung ,  Sung Chun Jun

IPC: H01L27/00 ,  H01L23/367 ,  H01L25/065 ,  H01L23/522 ,  H01L23/58 ,  H01L27/06

CPC classification number: H01L23/367 ,  H01L23/3677 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/585 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having improved heat-dissipation characteristics is capable effectively discharging heat that is generated inside the semiconductor device of a three-dimensional laminated structure, to the outside of the semiconductor device by utilizing an internal connector used during bonding.

公开(公告)号：US09934170B2

公开(公告)日：2018-04-03

申请号：US15108537

申请日：2014-11-27

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Seong Jun Park ,  Huy Chan Jung ,  Sang Wook Ahn

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/16

CPC classification number: G06F13/1605 ,  G06F13/1689

Abstract: The present invention relates to a technology enabling a normal access by controlling a read access through an arbiter in a circuit for controlling an access to memory to which clock signals are input through two ports, respectively for a read access to a single port memory. The present invention includes an arbiter that generates an internal clock signal through a state transition among a first state for generating a first clock signal, a second state for generating a second clock signal, a standby state and a neutral state when generating the internal clock signal for reading data from the memory on the basis of the first clock signal and the second clock signal, and a read end signal that is supplied from the memory.

公开(公告)号：US09478464B2

公开(公告)日：2016-10-25

申请号：US14888674

申请日：2014-04-30

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Heui Gyun Ahn ,  Sang Wook Ahn ,  Yong Woon Lee ,  Huy Chan Jung ,  Do Young Lee

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/683

CPC classification number: H01L21/76898 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/7684 ,  H01L2221/68327 ,  H01L2221/68359

Abstract: A method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon via (TSV) with achievement of an effective electrical insulation between the through-hole silicon via (TSV) and the silicon.

Abstract translation: 用于制造通孔硅通孔（TSV）的方法采用传统的沟槽绝缘工艺来容易地制造通孔硅通孔（TSV），从而实现通孔硅通孔（TSV）和通孔硅通孔（TSV）之间的有效电绝缘 硅。

公开(公告)号：US09406652B2

公开(公告)日：2016-08-02

申请号：US14891635

申请日：2014-05-12

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Sang Wook Ahn ,  Huy Chan Jung ,  Yong Woon Lee ,  Do Young Lee ,  Heui-Gyun Ahn

IPC: G11C5/06 ,  H01L25/065 ,  H01L23/528 ,  G11C7/06 ,  G11C7/10

CPC classification number: H01L25/0657 ,  G11C5/063 ,  G11C7/06 ,  G11C7/10 ,  G11C2207/005 ,  H01L23/49816 ,  H01L23/528 ,  H01L25/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A semiconductor memory is formed by stacking a plurality of substrates and memory cells on each substrate are connected by data dump lines. A switch may intervene between the memory cell and the data dump line. When data of each substrate is dumped by the data dump line, a problem of decrease in a speed and an increase in power consumption due to a parasitic component can be minimized. Further, a core circuit including the memory cell may be disposed on one substrate and a peripheral circuit unit may be disposed on the remaining substrates.

Abstract translation: 通过堆叠多个基板形成半导体存储器，并且通过数据转储线连接每个基板上的存储单元。 交换机可以介入存储器单元和数据转储线之间。 当每个基板的数据被数据转储线转储时，由于寄生成分引起的速度下降和功耗增加的问题可以被最小化。 此外，包括存储单元的核心电路可以设置在一个基板上，并且外围电路单元可以设置在剩余的基板上。

公开(公告)号：US20160267946A1

公开(公告)日：2016-09-15

申请号：US15032935

申请日：2014-10-27

Applicant: SILICONFILE TECHNOLOGIES INC.

Inventor： Sang Wook Ahn ,  Huy Chan Jung ,  Yong Woon Lee ,  Heui-Gyun Ahn ,  Do Young Lee

IPC: G11C5/02 ,  G11C8/06 ,  G11C8/10 ,  H01L25/065 ,  G11C5/06 ,  H01L23/48

CPC classification number: G11C5/025 ,  G11C5/063 ,  G11C8/06 ,  G11C8/10 ,  H01L23/48 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a stack memory device and a method for operating same. The stack memory device, according to the present invention, is provided with: a first memory chip in which first type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each first type memory cell; and a second memory chip in which second type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each second type memory cell, wherein first pads are connected to the dump lines of the first type memory cells and second pads are connected to the dump lines of the second type memory cells, the first pads and the second pads having one-to-one correspondence.

Abstract translation: 本发明提供了一种堆栈存储装置及其操作方法。 根据本发明的堆叠存储器件提供有：第一存储器芯片，其中第一类型存储器单元在行方向和列方向上重复布置，并且包括一个或多个单元阵列，其中转储线是 连接到每个第一类型存储单元; 以及第二存储器芯片，其中第二类型存储器单元在行方向和列方向上重复排列，并且包括一个或多个单元阵列，其中转储线连接到每个第二类型存储单元，其中第一焊盘被连接 到第一类型存储单元的转储线和第二焊盘连接到第二类型存储单元的转储线，第一焊盘和第二焊盘具有一一对应关系。