公开(公告)号：US10374549B2

公开(公告)日：2019-08-06

申请号：US15399059

申请日：2017-01-05

Applicant: SDRF EURL

Inventor： Biagio Bisanti ,  Eric Duvivier ,  Lorenzo Carpineto ,  Stefano Cipriani ,  Francesco Coppola ,  Gianni Puccio ,  Rémi Artinian ,  Francois Marot ,  Vanessa Bedero ,  Lysiane Koechlin

IPC: H03B5/04 ,  H03B5/12 ,  H03L7/099

Abstract: Variable frequency oscillators allowing wide tuning range and low phase noise is disclosed. In an illustrative embodiment, a first transistor has a first terminal (e.g. collector) connected to a reference voltage, and a second terminal (e.g. emitter) connected to a first terminal of a first current source and to ground. The first transistor further has a third terminal connected to a first inductor and to a first capacitor connected to the emitter of the first transistor and also to a second capacitor connected to ground. A second transistor is similarly constructed. In order to achieve a variable frequency oscillation between the emitters of the two transistors, a variable tank capacitor is connected between the inductors, forming a circuit connecting in series all passive components composing the LC tank, masking most of parasitic capacitances.

公开(公告)号：US10200049B2

公开(公告)日：2019-02-05

申请号：US15399040

申请日：2017-01-05

Applicant: SDRF EURL

Inventor： Biagio Bisanti ,  Eric Duvivier ,  Lorenzo Carpineto ,  Stefano Cipriani ,  Francesco Coppola ,  Gianni Puccio ,  Rémi Artinian ,  Francois Marot ,  Vanessa Bedero ,  Lysiane Koechlin

IPC: H03L7/07 ,  H03L7/23 ,  H03L7/093 ,  H03L7/099 ,  H03L7/185

Abstract: A multiloop PLL circuit comprising: a first PLL loop comprising a first VCO, a first phase detector having a first input receiving a reference frequency (Fref) and a second input receiving the output of a first programmable divider, which input receives the signal generated by the first VCO and a first loop filter connected between said first phase detector and said first VCO; at least one auxiliary PLL loop comprising a second VCO, a second phase detector, a second (R1) and a third (N1) programmable dividers, and a second loop filter a main loop for generating a desired output frequency Fout comprising a third VCO, a third phase detector, a fourth (Rn) and a fifth (Nn) programmable divider, a main loop filter and a mixer additional possible auxiliary PLL loop each comprising a forth VCO, a forth phase detector, a sixth (Ri) and a seventh (Ni) programmable divider, a third auxiliary loop filter and a mixer whereby the desired output frequency Fout is generated in accordance with the relation: Fout=(N1/R1+ . . . +Nn/Rn)*Fcro where N1 and R1 are the dividing values of the first auxiliary loop and Ni and Ri with i=2 . . . n−1 being the dividing ratios of any possible further auxiliary loop; and Fcro is the frequency generated by VCO, whereby the multiloop circuit is configured with dividing values which optimizes a cost function F.