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    Read bias adjustment for compensating threshold voltage shift due to lateral charge movement
    2.
    发明授权
    Read bias adjustment for compensating threshold voltage shift due to lateral charge movement 有权

    公开(公告)号：US10541035B1

    公开(公告)日：2020-01-21

    申请号：US16022373

    申请日：2018-06-28

    Applicant: SanDisk Technologies LLC

    Inventor： Ching-Huang Lu ,  Han-Ping Chen ,  Chung-Yao Pai ,  Yingda Dong

    IPC: G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

    Abstract: Apparatuses and techniques are provided for accurately reading memory cells by compensating for lateral charge diffusion between adjacent memory cells. A selected memory cell is read with a compensation which is based on classifying the threshold voltages of adjacent memory cells into bins. In one aspect, the compensation is based on the level of the current control gate voltage of the selected word line. In another aspect, the classifying of the threshold voltages of the adjacent memory cells can be a function of temperature. In another aspect, a memory cell can be read with compensation after a previous read operation without compensation results in an uncorrectable error. In another aspect, the classifying uses more bins for a selected edge word line.

    Reducing program disturb by modifying word line voltages at interface in two-tier stack during programming
    5.
    发明授权
    Reducing program disturb by modifying word line voltages at interface in two-tier stack during programming 有权

    公开(公告)号：US10438671B1

    公开(公告)日：2019-10-08

    申请号：US16015612

    申请日：2018-06-22

    Applicant: SanDisk Technologies LLC

    Inventor： Hong-Yan Chen ,  Yingda Dong

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C11/56

    Abstract: Techniques for reducing program disturb of memory cells which are formed in a two-tier stack, when a selected word line is in the upper tier. In one approach, at the start of the program phase of a program loop, voltages of word lines adjacent to the interface are increased to a pass voltage before voltages of remaining word lines are increased to a pass voltage. This delay provides time for residue electrons in the lower tier to move toward the drain end of a NAND string to reduce the likelihood of program disturb. In another approach, the voltages of the word lines adjacent to the interface are maintained at 0 V or other turn-off voltage during the program phase to block the passage of residue electrons from the lower tier to the upper tier.

    Grouping memory cells into sub-blocks for program speed uniformity
    7.
    发明授权
    Grouping memory cells into sub-blocks for program speed uniformity 有权

    公开(公告)号：US10431313B2

    公开(公告)日：2019-10-01

    申请号：US15923064

    申请日：2018-03-16

    Applicant: SanDisk Technologies LLC

    Inventor： Zhengyi Zhang ,  Yingda Dong ,  James Kai ,  Johann Alsmeier

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/28

    Abstract: A three-dimensional stacked memory device is configured to provide uniform programming speeds of different sets of memory strings formed in memory holes. In a process for removing sacrificial material from word line layers, a block oxide layer in the memory holes is etched away relatively more when the memory hole is relatively closer to an edge of the word line layers where an etchant is introduced. A thinner block oxide layer is associated with a faster programming speed. To compensate, memory strings at the edges of the word line layers are programmed together, separate from the programming of interior memory strings. A program operation can use a higher initial program voltage for programming the interior memory strings compared to the edge memory strings.

    THREE-DIMENSIONAL FLAT INVERSE NAND MEMORY DEVICE AND METHOD OF MAKING THE SAME
    8.
    发明申请
    THREE-DIMENSIONAL FLAT INVERSE NAND MEMORY DEVICE AND METHOD OF MAKING THE SAME 审中-公开

    公开(公告)号：US20190221575A1

    公开(公告)日：2019-07-18

    申请号：US15971525

    申请日：2018-05-04

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Yingda Dong ,  Yangyin Chen ,  James Kai

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/06 ,  H01L29/20 ,  G11C16/04 ,  H01L21/02

    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart among one another by line trenches and a two-dimensional array of memory stack structures and a two-dimensional array of dielectric pillar structures located in the line trenches. Each line trench is filled with laterally alternating sequence of memory stack structures and dielectric pillar structures. Each memory stack structure contains a vertical semiconductor channel, a pair of blocking dielectrics contacting outer sidewalls of the vertical semiconductor channel, a pair of charge storage layers contacting outer sidewalls of the pair of blocking dielectrics, and a pair of tunneling dielectrics contacting outer sidewalls of the pair of charge storage layers.

    NAND boosting using dynamic ramping of word line voltages
    9.
    发明授权
    NAND boosting using dynamic ramping of word line voltages 有权

    公开(公告)号：US10297329B2

    公开(公告)日：2019-05-21

    申请号：US15352390

    申请日：2016-11-15

    Applicant: SanDisk Technologies LLC

    Inventor： Peter Rabkin ,  Yingda Dong ,  Masaaki Higashitani

    IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

    Abstract: Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the memory array.

    Reducing Hot Electron Injection Type Of Read Disturb In 3D Memory Device During Signal Switching Transients
    10.
    发明申请
    Reducing Hot Electron Injection Type Of Read Disturb In 3D Memory Device During Signal Switching Transients 审中-公开

    公开(公告)号：US20190074062A1

    公开(公告)日：2019-03-07

    申请号：US15694008

    申请日：2017-09-01

    Applicant: SanDisk Technologies LLC

    Inventor： Hong-Yan Chen ,  Wei Zhao ,  Ching-Huang Lu ,  Yingda Dong

    IPC: G11C16/08 ,  G11C16/04

    Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. Select gate transistors are transitioned to a conductive state one or more time during a sensing process, at the drain and/or source ends of the memory strings in an unselected sub-block. The transitioning can occur periodically, multiple times during the sensing process. When the select gate transistors are in a conductive state, accumulated holes in the channel can be removed. This help provide a faster decrease of the channel potential when the unselected word line voltages are ramped down at the end of the sensing process. The duration of a disturb-inducing channel gradient which is created next to the edge data memory cell is reduced so that read disturb of this cell is also reduced.

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