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公开(公告)号：US20150154109A1
公开(公告)日：2015-06-04
申请号：US14095294
申请日：2013-12-03
Applicant: SanDisk Technologies Inc.
Inventor： Mark Fiterman , Yoav Weinberg , Itai Dror
CPC classification number: G06F12/0246 , G06F12/0868 , G06F12/0886 , G06F12/0895 , G06F2212/7208
Abstract: A memory system comprising a non-volatile memory and a controller in communication with the non-volatile memory is disclosed. The controller may include a central processing unit (“CPU”) and an internal cache in communication with the CPU via a plurality of cache lines. The CPU is configured to utilize a first subset of the plurality of cache lines when accessing data stored in the internal cache at a first resolution. Additionally, the CPU is configured to utilize a second subset of the plurality of cache lines when accessing data stored in the internal case at a second resolution, where the first and second resolutions are different resolutions.
Abstract translation: 公开了一种包括非易失性存储器和与非易失性存储器通信的控制器的存储器系统。 控制器可以包括经由多个高速缓存行与CPU通信的中央处理单元（“CPU”）和内部高速缓存。 当以第一分辨率访问存储在内部高速缓存中的数据时，CPU被配置为利用多个高速缓存线的第一子集。 此外，CPU被配置为当以第二分辨率访问存储在内部情况中的数据时，利用多条高速缓存行的第二子集，其中第一和第二分辨率是不同的分辨率。
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公开(公告)号：US09886342B2
公开(公告)日：2018-02-06
申请号：US14925676
申请日：2015-10-28
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Yuri Ryabinin , Eran Banani , Yan Dumchin , Mark Naumenko , Alexander Mostovoy , Mark Fiterman
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1012 , G11C29/52 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3723 , H03M13/612 , H03M13/6325
Abstract: A data storage device may include a non-volatile memory and a controller. According to a first aspect, a bit error rate (BER) estimate may be determined at a memory interface of the controller based on hard bit data from the non-volatile memory. The BER estimate may be used to determine, prior to transfer of the hard bit data to an error correction coding (ECC) decoder of the controller, whether to request transfer of soft bit data from the non-volatile memory. According to a second aspect, the ECC decoder may be instructed to initiate decoding of a codeword or sub code using a particular operating mode based on the BER estimate for the codeword or sub code. According to a third aspect, sub codes of an ECC codeword may be reordered based on BER estimates for the sub codes, and the reordered sub codes may be provided to the ECC decoder.
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公开(公告)号：US09507706B2
公开(公告)日：2016-11-29
申请号：US14095294
申请日：2013-12-03
Applicant: SanDisk Technologies Inc.
Inventor： Mark Fiterman , Yoav Weinberg , Itai Dror
CPC classification number: G06F12/0246 , G06F12/0868 , G06F12/0886 , G06F12/0895 , G06F2212/7208
Abstract: A memory system comprising a non-volatile memory and a controller in communication with the non-volatile memory is disclosed. The controller may include a central processing unit (“CPU”) and an internal cache in communication with the CPU via a plurality of cache lines. The CPU is configured to utilize a first subset of the plurality of cache lines when accessing data stored in the internal cache at a first resolution. Additionally, the CPU is configured to utilize a second subset of the plurality of cache lines when accessing data stored in the internal case at a second resolution, where the first and second resolutions are different resolutions.
Abstract translation: 公开了一种包括非易失性存储器和与非易失性存储器通信的控制器的存储器系统。 控制器可以包括经由多个高速缓存行与CPU通信的中央处理单元（“CPU”）和内部高速缓存。 当以第一分辨率访问存储在内部高速缓存中的数据时，CPU被配置为利用多个高速缓存线的第一子集。 此外，CPU被配置为当以第二分辨率访问存储在内部情况中的数据时，利用多条高速缓存行的第二子集，其中第一和第二分辨率是不同的分辨率。
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公开(公告)号：US20170123898A1
公开(公告)日：2017-05-04
申请号：US14925676
申请日：2015-10-28
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： Yuri Ryabinin , Eran Banani , Yan Dumchin , Mark Naumenko , Alexander Mostovoy , Mark Fiterman
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1012 , G11C29/52 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/3723 , H03M13/612 , H03M13/6325
Abstract: A data storage device may include a non-volatile memory and a controller. According to a first aspect, a bit error rate (BER) estimate may be determined at a memory interface of the controller based on hard bit data from the non-volatile memory. The BER estimate may be used to determine, prior to transfer of the hard bit data to an error correction coding (ECC) decoder of the controller, whether to request transfer of soft bit data from the non-volatile memory. According to a second aspect, the ECC decoder may be instructed to initiate decoding of a codeword or sub code using a particular operating mode based on the BER estimate for the codeword or sub code. According to a third aspect, sub codes of an ECC codeword may be reordered based on BER estimates for the sub codes, and the reordered sub codes may be provided to the ECC decoder.
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