公开(公告)号：US5918074A

公开(公告)日：1999-06-29

申请号：US900757

申请日：1997-07-25

Applicant: Tim Wright ,  Peter Marconi ,  Richard Conlin ,  Zbigniew Opalka

Inventor： Tim Wright ,  Peter Marconi ,  Richard Conlin ,  Zbigniew Opalka

IPC: G06F13/12 ,  H04L12/56 ,  G06F13/00

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L2012/5638 ,  H04L2012/5681

Abstract: A novel networking architecture and technique for reducing system latency caused, at least in part, by access contention for usage of common bus and memory facilities, wherein a separate data processing and queue management forwarding engine and queue manager are provided for each I/O module to process packet/cell control information and delivers queuing along a separate path that eliminates contention with other resources and is separate from the transfer of packet/cell data into and from the memory.

Abstract translation: 一种用于减少系统延迟的新型网络架构和技术，至少部分地由于对公共总线和存储设备的使用的访问争用而引起，其中为每个I / O模块提供单独的数据处理和队列管理转发引擎和队列管理器 处理分组/小区控制信息，并且沿着消除与其他资源的争用的单独路径递送排队，并且与从存储器传入分组/小区数据分离。

公开(公告)号：US07673206B2

公开(公告)日：2010-03-02

申请号：US11901184

申请日：2007-09-14

Applicant: Richard Conlin

Inventor： Richard Conlin

IPC: G01R31/28

CPC classification number: G06F11/2236 ,  G01R31/318533

Abstract: The present invention provides a method and system for routing a group of scan chains to a group of processor resources in a semiconductor chip. The group of processor resources is arranged in rows or columns. The group of processor resources in each row or column is connected through a plurality of scan chains. The first processor resource in each row or column is connected to input scan-chain pins, and the last processor resource in each row or column is connected to output scan-chain pins. A test-pattern generator, generating test signals, sends the test signals to the group of processor resources by using the group of scan chains within the semiconductor chip. The responses of the processor resources corresponding to the test signals are analyzed to detect and locate any error in the manufacture of the semiconductor chip.

Abstract translation: 本发明提供一种用于将一组扫描链路由到半导体芯片中的一组处理器资源的方法和系统。 处理器资源组按行或列排列。 每行或列中的处理器资源组通过多个扫描链连接。 每行或每列中的第一个处理器资源连接到输入扫描链引脚，每行或列中的最后一个处理器资源连接到输出扫描链引脚。 产生测试信号的测试模式发生器通过使用半导体芯片内的扫描链组将测试信号发送到处理器资源组。 分析对应于测试信号的处理器资源的响应，以检测和定位半导体芯片的制造中的任何错误。

公开(公告)号：US20090077437A1

公开(公告)日：2009-03-19

申请号：US11901184

申请日：2007-09-14

Applicant: Richard Conlin

Inventor： Richard Conlin

IPC: G06F11/25 ,  G06F11/263

CPC classification number: G06F11/2236 ,  G01R31/318533

Abstract: The present invention provides a method and system for routing a group of scan chains to a group of processor resources in a semiconductor chip. The group of processor resources is arranged in rows or columns. The group of processor resources in each row or column is connected through a plurality of scan chains. The first processor resource in each row or column is connected to input scan-chain pins, and the last processor resource in each row or column is connected to output scan-chain pins. A test-pattern generator, generating test signals, sends the test signals to the group of processor resources by using the group of scan chains within the semiconductor chip. The responses of the processor resources corresponding to the test signals are analyzed to detect and locate any error in the manufacture of the semiconductor chip.

Abstract translation: 本发明提供一种用于将一组扫描链路由到半导体芯片中的一组处理器资源的方法和系统。 处理器资源组按行或列排列。 每行或列中的处理器资源组通过多个扫描链连接。 每行或每列中的第一个处理器资源连接到输入扫描链引脚，每行或列中的最后一个处理器资源连接到输出扫描链引脚。 产生测试信号的测试模式发生器通过使用半导体芯片内的扫描链组将测试信号发送到处理器资源组。 分析对应于测试信号的处理器资源的响应，以检测和定位半导体芯片的制造中的任何错误。

公开(公告)号：US06212597B1

公开(公告)日：2001-04-03

申请号：US08901502

申请日：1997-07-28

Applicant: Richard Conlin ,  Tim Wright ,  Peter Marconi ,  Mukesh Chatter

Inventor： Richard Conlin ,  Tim Wright ,  Peter Marconi ,  Mukesh Chatter

IPC: G06F1200

CPC classification number: G06F13/16

Abstract: Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.

Abstract translation: 通过提供与其他这样的资源发送的系统I / O资源消息和DRAM阵列内的消息位置进行通信，并且进一步提供有效的内部数据，提供多端口内部缓存DRAM等的性能的装置和方法 总线用于适应小型和大型数据传输单元。

公开(公告)号：US08738860B1

公开(公告)日：2014-05-27

申请号：US13280927

申请日：2011-10-25

Applicant: Patrick Robert Griffin ,  Mathew Hostetter ,  Anant Agarwal ,  Chyi-Chang Miao ,  Christopher D. Metcalf ,  Bruce Edwards ,  Carl G. Ramey ,  Mark B. Rosenbluth ,  David M. Wentzlaff ,  Christopher J. Jackson ,  Ben Harrison ,  Kenneth M. Steele ,  John Amann ,  Shane Bell ,  Richard Conlin ,  Kevin Joyce ,  Christine Deignan ,  Liewei Bao ,  Matthew Mattina ,  Ian Rudolf Bratt ,  Richard Schooler

Inventor： Patrick Robert Griffin ,  Mathew Hostetter ,  Anant Agarwal ,  Chyi-Chang Miao ,  Christopher D. Metcalf ,  Bruce Edwards ,  Carl G. Ramey ,  Mark B. Rosenbluth ,  David M. Wentzlaff ,  Christopher J. Jackson ,  Ben Harrison ,  Kenneth M. Steele ,  John Amann ,  Shane Bell ,  Richard Conlin ,  Kevin Joyce ,  Christine Deignan ,  Liewei Bao ,  Matthew Mattina ,  Ian Rudolf Bratt ,  Richard Schooler

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/1441

Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Abstract translation: 计算系统包括一个或多个核心。 每个核心包括处理器。 在一些实现中，每个处理器耦合到核心之间的通信网络。 在一些实现中，每个核心中的交换机包括交换电路，用于将通过数据路径从其他核到达处理器的数据路径接收的数据转发到其他核心的交换机，并将从处​​理器接收的数据转发到其他核心的交换机。

公开(公告)号：US20070029398A1

公开(公告)日：2007-02-08

申请号：US11197479

申请日：2005-08-05

Applicant: Richard Conlin

Inventor： Richard Conlin

IPC: G05D23/02 ,  G05D23/08 ,  G05D23/12

CPC classification number: F16K31/002 ,  G05D23/022 ,  Y10T137/7737

Abstract: A thermal by-pass valve for fluids includes a sleeve having an inlet opening, and two outlet openings. One of the outlet openings functions as a by-pass opening. A bi-metallic metal coil is enclosed within the sleeve. The coil has one end securely attached to a cap, which cap incorporates an inlet for a fluid. The cap is attached to the inlet opening of the sleeve. The bi-metallic coil is designed to rotate the sleeve when the temperature of the fluid exceeds or drops below a designated threshold temperature.

Abstract translation: 用于流体的热旁通阀包括具有入口开口的套筒和两个出口开口。 出口之一作为旁路开口。 双金属线圈封装在套管内。 线圈具有牢固地附接到盖的一端，该盖包括用于流体的入口。 盖子连接到套筒的入口开口。 双金属线圈设计成当流体的温度超过或低于指定的临界温度时旋转套筒。