公开(公告)号：US09854295B2

公开(公告)日：2017-12-26

申请号：US15587682

申请日：2017-05-05

Applicant: Renesas Electronics Corporation

Inventor： Masami Tako ,  Naohiro Nishikawa ,  Yuichi Takagi

IPC: H04N21/43 ,  G11B27/00 ,  H04N21/44 ,  H04N21/4385 ,  H04N21/8547 ,  G09G3/36

CPC classification number: H04N21/4307 ,  G06F3/14 ,  G09G3/36 ,  G09G2360/12 ,  G11B27/005 ,  H04N21/43 ,  H04N21/4385 ,  H04N21/44004 ,  H04N21/8547

Abstract: A data processing device, includes a bus, a demultiplexer which receives content including video data and audio data. A memory interface is coupled to the bus, and is connectable to a memory for temporarily accumulating the video data and the audio data output from the demultiplexer.

公开(公告)号：US09723355B2

公开(公告)日：2017-08-01

申请号：US15361566

申请日：2016-11-28

Applicant: Renesas Electronics Corporation

Inventor： Masami Tako ,  Naohiro Nishikawa ,  Yuichi Takagi

IPC: H04N21/43 ,  G06F3/14 ,  H04N21/44 ,  H04N21/4385 ,  H04N21/8547 ,  G09G3/36

CPC classification number: H04N21/4307 ,  G06F3/14 ,  G09G3/36 ,  G09G2360/12 ,  G11B27/005 ,  H04N21/43 ,  H04N21/4385 ,  H04N21/44004 ,  H04N21/8547

Abstract: A data processing device, includes a bus, a demultiplexer which is coupled to the bus, and which receives a content including video data and audio data. A memory interface which is coupled to the bus, and which is connectable to a memory for temporarily accumulating the video data and the audio data output from the demultiplexer in accordance with a delay amount.

公开(公告)号：US20170238044A1

公开(公告)日：2017-08-17

申请号：US15587682

申请日：2017-05-05

Applicant: Renesas Electronics Corporation

Inventor： Masami TAKO ,  Naohiro Nishikawa ,  Yuichi Takagi

IPC: H04N21/43 ,  H04N21/8547 ,  H04N21/4385 ,  G11B27/00 ,  H04N21/44

CPC classification number: H04N21/4307 ,  G06F3/14 ,  G09G3/36 ,  G09G2360/12 ,  G11B27/005 ,  H04N21/43 ,  H04N21/4385 ,  H04N21/44004 ,  H04N21/8547

Abstract: A data processing device, includes a bus, a demultiplexer which receives content including video data and audio data. A memory interface is coupled to the bus, and is connectable to a memory for temporarily accumulating the video data and the audio data output from the demultiplexer.

公开(公告)号：US10200741B2

公开(公告)日：2019-02-05

申请号：US15817701

申请日：2017-11-20

Applicant: Renesas Electronics Corporation

Inventor： Masami Tako ,  Naohiro Nishikawa ,  Yuichi Takagi

IPC: H04N21/43 ,  H04N21/44 ,  G06F3/14 ,  H04N21/4385 ,  H04N21/8547 ,  G11B27/00 ,  G09G3/36

Abstract: A data processing device, includes a bus, a demultiplexer which receives content including video data and audio data.A memory interface which is coupled to the bus, and which is connectable to a memory for temporarily accumulating the video data and the audio data output from the demultiplexer.

公开(公告)号：US10659722B2

公开(公告)日：2020-05-19

申请号：US16410603

申请日：2019-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuichi Takagi ,  Ren Imaoka

IPC: H04N7/01

Abstract: A video signal receiving apparatus receives a first and second video signals for transmitting a same video content. When determining a size adjustment amount of a second video included in the second video signal, the video signal receiving apparatus performs scaling processing on a second image included in the second video signal to generate a scaling image and performs shift processing on the second image to generate a shift image. The video signal receiving apparatus calculates a similarity degree between a first image included in the first video signal and the scaling image, calculates a similarity degree between the first image and the shift image, and uses the scaling image or the shift image having the higher calculated similarity degree as an image to be subjected to the next scaling processing and the next shift processing.

公开(公告)号：US09521450B2

公开(公告)日：2016-12-13

申请号：US14617780

申请日：2015-02-09

Applicant: Renesas Electronics Corporation

Inventor： Masami Tako ,  Naohiro Nishikawa ,  Yuichi Takagi

IPC: H04N21/43 ,  H04N21/44

CPC classification number: H04N21/4307 ,  G06F3/14 ,  G09G3/36 ,  G09G2360/12 ,  G11B27/005 ,  H04N21/43 ,  H04N21/4385 ,  H04N21/44004 ,  H04N21/8547

Abstract: At the time of device starting or channel switching in a content output device, even when buffering of a sufficiently large size is performed in order to address multimedia processing at the time of start of a device and content switching, slow reproduction in which video and audio are synchronized with each other can be performed without keeping a user waiting for a long time, and at an arbitrary reproduction rate with the extent of not giving the user feeling of unnaturalness. The broadcasting reception unit initializes the delay amount to a predetermined start value, then gradually increases it with lapse of time, and stops the increase when the delay amount reaches a predetermined end value. Video and audio are synchronously and slowly reproduced at a reproduction rate decided by an increment per unit time of the delay amount.

Abstract translation: 在内容输出装置中的装置开始或频道切换时，即使执行足够大尺寸的缓冲以便在设备启动时进行多媒体处理和内容切换，其中视频和音频 可以在不保持用户等待很长时间的情况下执行彼此同步，并且以不给予用户感觉不自然的程度以任意的再现速率进行。 广播接收单元将延迟量初始化为预定的起始值，然后随着时间的推移逐渐增加，并且当延迟量达到预定的结束值时停止增加。 视频和音频以由延迟量的每单位时间的增量决定的再现速率同步且缓慢地再现。