公开(公告)号：US11264087B2

公开(公告)日：2022-03-01

申请号：US16845929

申请日：2020-04-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshisato Yokoyama ,  Makoto Yabuuchi

IPC: G11C11/418 ,  G11C11/419

Abstract: A semiconductor device includes a first wiring having a first portion, a second portion, a third portion provided between the first portion and the second portion, memory cells connected to the third portion of the first wiring, a field effect transistor having a drain connected to the second portion, and a gate, and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion located nearest to the first portion and a fifth portion located nearest to the second portion. The first wiring further includes a sixth portion disposed between the first portion and the fourth portion. The memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.

公开(公告)号：US09830980B2

公开(公告)日：2017-11-28

申请号：US15465300

申请日：2017-03-21

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Miyanishi ,  Yuichiro Ishii ,  Yoshisato Yokoyama

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C29/02 ,  G11C29/04 ,  G11C29/06 ,  G11C29/34 ,  G11C29/46 ,  G11C29/48 ,  G11C29/50

Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed. An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.

公开(公告)号：US11081169B2

公开(公告)日：2021-08-03

申请号：US16577465

申请日：2019-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Daisuke Nakamura ,  Yoshisato Yokoyama

IPC: G11C11/412 ,  G11C11/417 ,  H01L27/02 ,  H01L27/11 ,  G11C11/419

Abstract: A semiconductor device has a first memory circuit comprising a first memory cell comprising a first field effect transistor, a second memory circuit comprising a second memory cell comprising a second field effect transistor, and a regulator for converting the first power supply potential to a second voltage value lower than the voltage value of the first power supply potential. The second gate length of the second field effect transistor is longer than the first gate length of the first field effect transistor, the first memory cell is supplied with a second power supply potential through regulator, and the second memory cell is supplied with a first power supply potential.

公开(公告)号：US10373675B2

公开(公告)日：2019-08-06

申请号：US15492147

申请日：2017-04-20

Applicant: Renesas Electronics Corporation

Inventor： Yoshisato Yokoyama ,  Yuichiro Ishii

IPC: G11C11/418 ,  G11C11/417 ,  G11C5/14

Abstract: A semiconductor storage device includes, a memory array, a plurality of memory cells provided in rows and columns, and a control circuit for controlling the memory array, each of the memory cells being a static-type memory cell comprising driving transistors, transfer transistors, and load elements.

公开(公告)号：US10109337B2

公开(公告)日：2018-10-23

申请号：US15613882

申请日：2017-06-05

Applicant: Renesas Electronics Corporation

Inventor： Yoshisato Yokoyama ,  Yoshikazu Saito ,  Shunya Nagata ,  Toshiaki Sano ,  Takeshi Hashizume

IPC: G11C7/00 ,  G11C11/405 ,  G11C7/06 ,  G11C8/16 ,  G11C11/406 ,  G11C11/408 ,  H03K19/177 ,  G11C29/02 ,  G11C29/32 ,  G11C29/12

Abstract: Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.

公开(公告)号：US10830814B2

公开(公告)日：2020-11-10

申请号：US16286447

申请日：2019-02-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshisato Yokoyama

IPC: G11C11/00 ,  G01R31/317 ,  G11C11/418 ,  G11C11/419 ,  G11C11/412

Abstract: A semiconductor device includes a memory cell array, a plurality of word lines, a plurality of bit line pairs, a column selection circuit coupling a bit line pair in a selected column in the plurality of bit line pairs to first and second output signal lines on the basis of a column selection signal, and a sense amplifier amplifying the voltage difference between the first and second output signal lines. The semiconductor device further includes: a scan flip flop to which the data can be input via a scan chain; and a voltage setting circuit setting the first and second output signal lines to voltage according to the data held in the scan flip flop in a scan test.

公开(公告)号：US10811405B2

公开(公告)日：2020-10-20

申请号：US16528177

申请日：2019-07-31

Applicant: Renesas Electronics Corporation

Inventor： Yuta Yoshida ,  Makoto Yabuuchi ,  Yoshisato Yokoyama

IPC: H01L27/11 ,  H01L27/02 ,  G11C11/418 ,  G11C11/419 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate, a word line connected to the memory cell, and an auxiliary line connected to the word line.

公开(公告)号：US10552261B2

公开(公告)日：2020-02-04

申请号：US15984572

申请日：2018-05-21

Applicant: Renesas Electronics Corporation

Inventor： Takeshi Hashizume ,  Naoya Fujita ,  Shunya Nagata ,  Yoshisato Yokoyama ,  Katsumi Shinbo ,  Kouji Satou

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C11/413

Abstract: A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.

公开(公告)号：US10424575B2

公开(公告)日：2019-09-24

申请号：US15512933

申请日：2015-03-26

Applicant: Renesas Electronics Corporation

Inventor： Yuta Yoshida ,  Makoto Yabuuchi ,  Yoshisato Yokoyama

IPC: H01L27/11 ,  H01L27/02 ,  G11C11/418 ,  G11C11/419 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092

Abstract: Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.

公开(公告)号：US09711208B2

公开(公告)日：2017-07-18

申请号：US14878049

申请日：2015-10-08

Applicant: Renesas Electronics Corporation

Inventor： Yoshisato Yokoyama ,  Yuichiro Ishii

IPC: G11C11/417 ,  G11C5/14

CPC classification number: G11C11/418 ,  G11C5/148 ,  G11C11/417

Abstract: There is provided a semiconductor storage device in which memory cells can easily be set at a proper potential in standby mode, along with a reduction in the area of circuitry for controlling the potential of source lines of memory cells. A semiconductor storage device includes static-type memory cells and a control circuit. The control circuit includes a first switching transistor provided between a source line being coupled to a source electrode of driving transistors and a first voltage, a second switching transistor provided in parallel with the first switching transistor, and a source line potential control circuit which makes the first and second switching transistors conductive to couple the source line to the first voltage, when the memory cells are operating, and sets the first switching transistor non-conductive and sets a gate electrode of the second switching transistor coupled to the source line in standby mode.