公开(公告)号：US08717220B2

公开(公告)日：2014-05-06

申请号：US13306868

申请日：2011-11-29

Applicant: R. Jacob Baker

Inventor： R. Jacob Baker

IPC: H03M1/56

CPC classification number: G11C16/26 ,  G11C7/06 ,  H03M3/39 ,  H03M3/43 ,  H03M3/456

Abstract: Methods for reading a data location coupled to an electrical conductor. A counter receives a signal from an analog-to-digital converter coupled to the electrical conductor. The counter produces two or more counts, and in some embodiments, the counts are based in part on a variable reference voltage. An interfuser may be coupled to an output of the counter. The interfuser receives the two or more counts from the counter and reads data conveyed by the data location based on the two or more counts.

Abstract translation: 读取耦合到电导体的数据位置的方法。 计数器从耦合到电导体的模数转换器接收信号。 计数器产生两个或多个计数，并且在一些实施例中，计数部分地基于可变参考电压。 接口用户可以耦合到计数器的输出。 接口用户从计数器接收两个或多个计数，并且基于两个或更多个计数读取由数据位置传送的数据。

公开(公告)号：US08675413B2

公开(公告)日：2014-03-18

申请号：US13306848

申请日：2011-11-29

Applicant: R. Jacob Baker

Inventor： R. Jacob Baker

IPC: G11C11/34 ,  G11C7/02 ,  G11C7/04

CPC classification number: G11C16/06 ,  G11C5/147 ,  G11C7/02 ,  G11C7/067 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C13/0004 ,  G11C13/004 ,  H03M3/39 ,  H03M3/456 ,  H04N5/357 ,  H04N5/376

Abstract: Systems, methods, and devices are disclosed, including an electronic device that includes a first data location, a quantizing circuit, and a reference current source, all coupled to an electrical conductor. The reference current source may include a current mirror with a side coupled to the electrical conductor and a second data location coupled to another side of the current mirror.

Abstract translation: 公开了系统，方法和设备，包括包括第一数据位置，量化电路和参考电流源的电子设备，全部耦合到电导体。 参考电流源可以包括具有耦合到电导体的一侧的电流镜和耦合到电流镜的另一侧的第二数据位置。

公开(公告)号：US08582375B2

公开(公告)日：2013-11-12

申请号：US13486535

申请日：2012-06-01

Applicant: R. Jacob Baker

Inventor： R. Jacob Baker

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C5/147 ,  G11C7/065 ,  G11C7/16 ,  G11C8/08 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2211/5634 ,  G11C2211/5644 ,  H03M3/43 ,  H03M3/456

Abstract: A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs and an output. The circuit is configured to combine (add or subtract) input signals. The first input may be connected to the analog input. The delta-sigma modulator may also include an integrator connected to the output of the circuit, an analog-to-digital converter with an input connected to an output of the integrator and an output connected to the digital output, and a digital-to-analog converter with an input connected to the output of the analog-to-digital converter and an output connected to the second input of the circuit.

Abstract translation: 在某些实施例中，存储器件包括连接到位线的多个存储器元件和可以连接到位线的具有数字输出和模拟输入的Δ-Σ调制器。 在一些实施例中，Δ-Σ调制器包括具有第一和第二输入和输出的电路。 该电路被配置为组合（加或减）输入信号。 第一个输入可以连接到模拟输入。 Δ-Σ调制器还可以包括连接到电路的输出的积分器，具有连接到积分器的输出的输入和连接到数字输出的输出的模数转换器，以及数模转换器， 模拟转换器，其输入连接到模数转换器的输出端，输出端连接到电路的第二输入端。

公开(公告)号：US08581168B2

公开(公告)日：2013-11-12

申请号：US13074290

申请日：2011-03-29

Applicant: Lloyd F. Linder ,  Daniel Renner ,  Michael MacDougal ,  Jonathan Geske ,  R. Jacob Baker

Inventor： Lloyd F. Linder ,  Daniel Renner ,  Michael MacDougal ,  Jonathan Geske ,  R. Jacob Baker

IPC: H01L27/00 ,  G01J1/44

CPC classification number: H04N5/33 ,  F41G7/008 ,  F41G7/2253 ,  F41G7/226 ,  F41G7/2293 ,  H04N5/2256

Abstract: A single camera capable of capturing high speed laser return pulses for a target, as well as provide imaging information on the background of the target. This capability is enabled by having a read-out integrated circuit (ROIC) capable of extracting both types of information from a pixel of a focal plane array (FPA). Further, an ROIC topology that allows for the ability to distinguish between high frequency and low frequency signal paths, and provide supporting circuitry to process the two paths separately. One path may integrate the low frequency background scene to provide a high fidelity image of the scene. The second path may process high frequency noise and multiple laser pulse returns within a frame. These two paths may be combined to provide a background image with a superimposed laser return.

Abstract translation: 一个能够捕获目标的高速激光返回脉冲的单个相机，以及在目标的背景上提供成像信息。 通过具有能够从焦平面阵列（FPA）的像素中提取两种类型的信息的读出集成电路（ROIC）来实现该能力。 此外，ROIC拓扑允许区分高频和低频信号路径的能力，并提供支持电路来分别处理两个路径。 一个路径可以集成低频背景场景以提供场景的高保真图像。 第二路径可以处理高频噪声并且在一帧内处理多个激光脉冲返回。 这两个路径可以组合以提供具有叠加的激光返回的背景图像。

公开(公告)号：US20120098691A1

公开(公告)日：2012-04-26

申请号：US13342844

申请日：2012-01-03

Applicant: R. Jacob Baker

Inventor： R. Jacob Baker

IPC: H03M1/34

CPC classification number: H03M1/60 ,  G11C11/5642 ,  G11C16/26 ,  H03K3/0231

Abstract: Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first condition and generating a second value by sensing the data location under a second condition. The method may further include combining the first value with the second value to identify data conveyed by the data location.

Abstract translation: 用于从数据位置获取数据的系统，方法和设备。 该方法可以包括通过在第一条件下感测数据位置来产生第一值，并且通过在第二条件下感测数据位置来产生第二值。 该方法还可以包括将第一值与第二值组合以识别由数据位置传送的数据。

公开(公告)号：US08098180B2

公开(公告)日：2012-01-17

申请号：US12694991

申请日：2010-01-27

Applicant: R. Jacob Baker

Inventor： R. Jacob Baker

IPC: H03M1/12

CPC classification number: H03M1/504 ,  G11C7/02 ,  G11C7/04 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2211/5634 ,  G11C2211/5644 ,  H03M3/39 ,  H03M3/43 ,  H03M3/456

Abstract: A device that includes an internal data storage location coupled to an electrical conductor and an analog-to-digital converter coupled to the internal data storage location via the electrical conductor. In some embodiments, the analog-to-digital converter includes a comparator having an input coupled to the electrical conductor and a switch coupled to the electrical conductor.

Abstract translation: 一种包括耦合到电导体的内部数据存储位置和经由电导体耦合到内部数据存储位置的模拟 - 数字转换器的装置。 在一些实施例中，模数转换器包括具有耦合到电导体的输入和耦合到电导体的开关的比较器。

公开(公告)号：US20110261637A1

公开(公告)日：2011-10-27

申请号：US13082785

申请日：2011-04-08

Applicant: Qawi I. Harvard ,  Robert J. Drost ,  R. Jacob Baker

Inventor： Qawi I. Harvard ,  Robert J. Drost ,  R. Jacob Baker

IPC: G11C7/06

CPC classification number: G11C11/4091 ,  G11C7/1048 ,  G11C11/4096 ,  G11C2207/002

Abstract: A memory device with increased communication bandwidth is described. In this memory device, control logic routes data signals from a memory array using inactive bitlines in response to a read command. These data signals are then placed on an adjacent unused input/output (I/O) line or routing channel, as opposed to a proximate I/O line that is in use. For example, unused bitlines located on the top and bottom of the memory array may be used to route data signals to adjacent local I/O lines. In particular, the data signals can be placed on unused local I/O lines which are associated with adjacent bitline sense amplifiers. The resulting increased communication bandwidth can overcome the constraints imposed by the limited number of local I/O lines in the memory device without appreciably increasing the chip size, power consumption, or cost.

Abstract translation: 描述了具有增加的通信带宽的存储器件。 在该存储器件中，控制逻辑响应于读取命令，使用不活动位线从存储器阵列路由数据信号。 然后将这些数据信号放置在相邻的未使用的输入/输出（I / O）线路或路由通道上，而不是正在使用的近似I / O线。 例如，位于存储器阵列的顶部和底部的未使用的位线可以用于将数据信号路由到相邻的本地I / O线路。 特别地，数据信号可以放置在与相邻位线读出放大器相关联的未使用的本地I / O线上。 所产生的增加的通信带宽可以克服由有限数量的本地I / O线在存储器件中施加的约束，而不会明显增加芯片尺寸，功耗或成本。

公开(公告)号：US20110119519A1

公开(公告)日：2011-05-19

申请号：US13011191

申请日：2011-01-21

Applicant: Wen Li ,  Aaron Schoenfeld ,  R. Jacob Baker

Inventor： Wen Li ,  Aaron Schoenfeld ,  R. Jacob Baker

IPC: G06F1/12

CPC classification number: G11C7/1066 ,  G06F1/10 ,  G06F1/12 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  H03L7/0814

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract translation: 公开了一种用于补偿来自逻辑电路（例如存储器件）的用于同步输出信号（例如数据信号或定时信号）的本地处理的系统时钟的偏斜和不对称性的装置和方法。 公开了第一相位检测器，延迟锁定环（DLL）延迟元件和伴随电路的阵列，以与系统时钟XCLK信号的上升沿相位锁定输出信号的上升沿。 此外，公开了比较器电路，寄存器延迟，DLL延迟元件阵列和伴随电路，以从DQ信号的下降沿增加或减去延迟，以产生DQ信号的对称输出。

公开(公告)号：US07916054B2

公开(公告)日：2011-03-29

申请号：US12436778

申请日：2009-05-07

Applicant: R. Jacob Baker

Inventor： R. Jacob Baker

IPC: H03M3/00

CPC classification number: H03M3/47

Abstract: A K-Delta-1-Sigma modulator filters or integrates (Sigma) the difference (Delta) between K-feedback paths and an input signal. By using K-feedback paths the topology enables sample rates that are K times the clock frequency of any one feedback path. The sigma block can be implemented in a number of ways including an active or passive integrator or a filter with specific characteristics. When implemented as an integrator, the sigma block is common to all the feedback paths, so that the modulation noise is pushed to a portion of the spectrum where it can be reduced by filtering. The delta block can be implemented in a number of ways including analog adders or switched capacitors.

Abstract translation: K-Delta-1-Sigma调制器将K反馈路径和输入信号之间的差值（Delta）滤波或积分（Sigma）。 通过使用K反馈路径，拓扑使得采样速率是任何一个反馈路径的时钟频率的K倍。 西格玛块可以以多种方式实现，包括有源或无源积分器或具有特定特征的滤波器。 当实现为积分器时，西格玛块对于所有反馈路径是公共的，使得调制噪声被推送到频谱的一部分，其中可以通过滤波来减少调制噪声。 Δ块可以通过多种方式实现，包括模拟加法器或开关电容器。

公开(公告)号：US20110063930A1

公开(公告)日：2011-03-17

申请号：US12951997

申请日：2010-11-22

Applicant: R. Jacob Baker

Inventor： R. Jacob Baker

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C5/147 ,  G11C7/065 ,  G11C7/16 ,  G11C8/08 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2211/5634 ,  G11C2211/5644 ,  H03M3/43 ,  H03M3/456

Abstract: A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs and an output. The circuit is configured to combined (add or subtract) input signals. The first input may be connected to the analog input. The delta-sigma modulator may also include an integrator connected to the output of the circuit, an analog-to-digital converter with an input connected to an output of the integrator and an output connected to the digital output, and a digital-to-analog converter with an input connected to the output of the analog-to-digital converter and an output connected to the second input of the circuit.

Abstract translation: 在某些实施例中，存储器件包括连接到位线的多个存储器元件和可以连接到位线的具有数字输出和模拟输入的Δ-Σ调制器。 在一些实施例中，Δ-Σ调制器包括具有第一和第二输入和输出的电路。 该电路被配置为组合（加或减）输入信号。 第一个输入可以连接到模拟输入。 Δ-Σ调制器还可以包括连接到电路的输出的积分器，具有连接到积分器的输出的输入和连接到数字输出的输出的模数转换器，以及数模转换器， 模拟转换器，其输入连接到模数转换器的输出端，输出端连接到电路的第二输入端。