公开(公告)号：US20170125152A1

公开(公告)日：2017-05-04

申请号：US14931659

申请日：2015-11-03

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Charles David Paynter ,  Ryan David Lane

IPC: H01F27/28 ,  H01F41/04 ,  H05K1/18 ,  H01F27/29

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F17/02 ,  H01F27/29 ,  H01F41/041 ,  H01F2027/2809 ,  H05K1/18

Abstract: A toroid inductor includes a plurality of first turns configured in a first ring shape and a plurality of second turns configured in a second ring shape. The plurality of first turns includes a plurality of first upper interconnects, a plurality of first lower interconnects, and a plurality of first vias coupled to the plurality of first upper interconnects and to the plurality of first lower interconnects. The plurality of second turns is at least partially intertwined with the plurality of first turns. The plurality of second turns includes a plurality of second upper interconnects, a plurality of second lower interconnects, and a plurality of second vias coupled to the plurality of second upper interconnects and to the plurality of second lower interconnects.

公开(公告)号：US09484281B2

公开(公告)日：2016-11-01

申请号：US14459319

申请日：2014-08-14

Applicant: QUALCOMM Incorporated

Inventor： Ryan David Lane ,  Charles David Paynter

IPC: H01L23/02 ,  H01L23/367 ,  H01L23/00 ,  H01L25/03 ,  H01L25/10 ,  H01L25/18 ,  H01L25/065 ,  H01L23/373 ,  H01L23/42 ,  H01L23/433

CPC classification number: H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/4334 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package on package semiconductor structure includes a first package positioned above a first surface of a substrate, a second package positioned above the first package, and a first thermal element positioned between the first package and the second package, wherein the first thermal element is separated from the second package by an air gap and the thermal element provides a heat path for heat generated by the first package.

Abstract translation: 封装半导体结构上的封装包括位于衬底的第一表面上方的第一封装，位于第一封装之上的第二封装以及位于第一封装与第二封装之间的第一热元件，其中第一热元件分离 从第二包装通过气隙，并且热元件为由第一包装产生的热量提供热路径。

公开(公告)号：US20160020193A1

公开(公告)日：2016-01-21

申请号：US14334521

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Jong-Hoon Lee ,  Young Kyu Song ,  Daeik Daniel Kim ,  Jung Ho Yoon ,  Uei-Ming Jow ,  Mario Francisco Velez ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L25/065 ,  H01L25/00 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract translation: 一些特征涉及包括衬底，第一管芯，第一封装层，第一再分配部分，第二管芯，第二封装层和第二封装层的集成器件（例如，封装封装（PoP）器件） 第二再分配部分。 基板包括第一表面和第二表面。 基板包括电容器。 第一管芯耦合到衬底的第一表面。 第一封装层封装第一裸片。 第一再分配部分耦合到第一封装。 第二管芯耦合到衬底的第二表面。 第二封装层封装第二管芯。 第二再分配部分耦合到第二封装层。

公开(公告)号：US09153560B2

公开(公告)日：2015-10-06

申请号：US14268974

申请日：2014-05-02

Applicant: QUALCOMM Incorporated

Inventor： Ryan David Lane ,  Charles David Paynter ,  David Ian West

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/014 ,  H01L2924/00

Abstract: Some features pertain to an integrated device that includes a first package, a set of interconnects, and a second package. The first package includes a first substrate comprising a first surface and a second surface. The first package includes a redistribution portion comprising a redistribution layer. The first package includes a first die coupled to the first surface of the first substrate. The set of interconnects is coupled to the redistribution portion of the first package. The second package is coupled to the first package through the set of interconnects. The second package includes a second substrate comprising a first surface and a second surface; and a second die coupled to the first surface of the second substrate, where the second die is electrically coupled to the first die through the second substrate of the second package, the set of interconnects, and the redistribution portion of the first package.

Abstract translation: 一些特征涉及包括第一封装，一组互连和第二封装的集成器件。 第一包装包括包括第一表面和第二表面的第一基底。 第一包装包括重分配部分，其包括再分配层。 第一封装包括耦合到第一衬底的第一表面的第一裸片。 该组互连耦合到第一封装的再分配部分。 第二包通过一组互连耦合到第一包装。 第二包装包括包括第一表面和第二表面的第二基底; 以及第二管芯，其耦合到所述第二衬底的所述第一表面，其中所述第二管芯通过所述第二封装的所述第二衬底，所述一组互连和所述第一封装的再分配部分电耦合到所述第一管芯。

公开(公告)号：US20150048480A1

公开(公告)日：2015-02-19

申请号：US13968627

申请日：2013-08-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L23/498 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/49827 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/642 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/16225 ,  H01L2225/06572 ,  H01L2924/19105

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract translation: 一些新颖的特征涉及一种半导体器件，其包括衬底，穿过衬底的第一腔体。 第一腔被配置为被互连材料（例如，焊球）占据。 衬底还包括耦合到第一腔的第一侧壁的第一金属层。 衬底还包括在衬底的第一表面上的第一集成无源器件（IPD），第一IPD耦合到第一金属层。 在一些实施方案中，基底是玻璃基底。 在一些实现中，第一IPD是至少一个电容器，电感器和/或电阻器中的一个。 在一些实施方式中，半导体器件还包括在衬底的第二表面上的第二集成无源器件（IPD）。 第二IPD耦合到第一金属层。

公开(公告)号：US10008316B2

公开(公告)日：2018-06-26

申请号：US14229367

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Siamak Fazelpour ,  Charles David Paynter ,  Ryan David Lane

IPC: H01F5/00 ,  H01F27/28 ,  H01F17/00 ,  H01L23/498 ,  H01L23/64 ,  H01L49/02

CPC classification number: H01F17/0013 ,  H01F2017/002 ,  H01F2017/0066 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011

Abstract: Some novel features pertain to a package substrate that includes a core layer, a first via, a first dielectric layer, and a first inductor. The core layer includes a first surface and a second surface. The first via is located in the core layer. The first dielectric layer is coupled to the first surface of the core layer. The first inductor is located in the first dielectric layer. The first inductor is coupled to the first via in the core layer. The first inductor is configured to generate a magnetic field that laterally traverses the package substrate. In some implementations, the package substrate further includes a first pad coupled to the first inductor, wherein the first pad is configured to couple to a solder ball. In some implementations, the package substrate includes a second via located in the core layer, and a second inductor located in the first dielectric layer.

公开(公告)号：US09577025B2

公开(公告)日：2017-02-21

申请号：US14181522

申请日：2014-02-14

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ryan David Lane ,  Glenn David Raskin ,  Shree Krishna Pandey

IPC: H01L49/02 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/1205

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, and a redistribution portion coupled to one of the metal layers. The redistribution portion includes a first metal redistribution layer, an insulation layer coupled to the first metal redistribution layer, and a second metal redistribution layer coupled to the insulation layer. The first metal redistribution layer, the insulation layer, and the second metal redistribution layer are configured to operate as a capacitor in the integrated device. In some implementations, the capacitor is a metal-insulator-metal (MIM) capacitor.

Abstract translation: 一些特征涉及包括衬底，耦合到衬底的几个金属层，耦合到衬底的几个电介质层和耦合到金属层之一的再分配部分的集成器件。 再分配部分包括第一金属再分布层，耦合到第一金属再分布层的绝缘层和耦合到绝缘层的第二金属再分配层。 第一金属再分布层，绝缘层和第二金属再分配层被配置为在集成器件中作为电容器工作。 在一些实施方案中，电容器是金属 - 绝缘体 - 金属（MIM）电容器。

公开(公告)号：US09449762B2

公开(公告)日：2016-09-20

申请号：US14272356

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H05K1/03 ,  H01G4/236 ,  H01G2/02 ,  H05K1/18 ,  H05K1/11 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H01G4/224 ,  H05K3/46 ,  H01G2/10 ,  H05K1/02

CPC classification number: H01G4/236 ,  H01G2/02 ,  H01G2/106 ,  H01G4/224 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/42

Abstract: Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

Abstract translation: 一些新颖的特征涉及包括具有等效串联电阻（ESR）控制的嵌入式封装衬底（EPS）电容器的衬底的封装衬底。 EPS电容器包括由电介质或绝缘薄膜材料隔开的两个导电电极和位于将电极连接到通孔的每个电极顶部的等效串联电阻（ESR）控制结构。 ESR控制结构可以包括金属层，电介质层和嵌入金属柱组中的一组金属柱，其嵌入电介质层并在电极和金属层之间延伸。 具有ESR控制结构的EPS电容器形成可嵌入封装衬底的ESR可配置EPS电容器。

公开(公告)号：US20150206854A1

公开(公告)日：2015-07-23

申请号：US14268974

申请日：2014-05-02

Applicant: QUALCOMM Incorporated

Inventor： Ryan David Lane ,  Charles David Paynter ,  David Ian West

IPC: H01L25/065 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/014 ,  H01L2924/00

Abstract: Some features pertain to an integrated device that includes a first package, a set of interconnects, and a second package. The first package includes a first substrate comprising a first surface and a second surface. The first package includes a redistribution portion comprising a redistribution layer. The first package includes a first die coupled to the first surface of the first substrate. The set of interconnects is coupled to the redistribution portion of the first package. The second package is coupled to the first package through the set of interconnects. The second package includes a second substrate comprising a first surface and a second surface; and a second die coupled to the first surface of the second substrate, where the second die is electrically coupled to the first die through the second substrate of the second package, the set of interconnects, and the redistribution portion of the first package.

Abstract translation: 一些特征涉及包括第一封装，一组互连和第二封装的集成器件。 第一包装包括包括第一表面和第二表面的第一基底。 第一包装包括重分配部分，其包括再分配层。 第一封装包括耦合到第一衬底的第一表面的第一裸片。 该组互连耦合到第一封装的再分配部分。 第二包通过一组互连耦合到第一包装。 第二包装包括包括第一表面和第二表面的第二基底; 以及第二管芯，其耦合到所述第二衬底的所述第一表面，其中所述第二管芯通过所述第二封装的所述第二衬底，所述一组互连和所述第一封装的再分配部分电耦合到所述第一管芯。

公开(公告)号：US20150115403A1

公开(公告)日：2015-04-30

申请号：US14063934

申请日：2013-10-25

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Daeik Daniel Kim ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane ,  Mario Francisco Velez ,  Chengjie Zuo ,  Changhan Hobie Yun

IPC: H01L49/02

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

Abstract translation: 一些新颖的特征涉及包括衬底，通过衬底的第一腔和围绕衬底的第一腔配置的环形电感器的集成器件。 环形电感器包括围绕第一腔配置的一组绕组。 该组绕组包括在衬底的第一表面上的第一组互连，一组通过衬底通孔（TSV）和在衬底的第二表面上的第二组互连。 第一组互连通过集合TSV耦合到第二组互连。 在一些实施方案中，集成器件还包括位于第一腔内的互连材料（例如，焊球）。 互连材料被配置为将管芯耦合到印刷电路板。 在一些实施方案中，互连材料是环形电感器的一部分。