公开(公告)号：US20220406607A1

公开(公告)日：2022-12-22

申请号：US17824287

申请日：2022-05-25

Applicant: Power Integrations, Inc.

Inventor： Alexey Kudymov ,  LinLin Liu ,  Jamal Ramdani

IPC: H01L21/285 ,  H01L29/20 ,  H01L29/66 ,  H01L29/417 ,  H01L29/778 ,  H01L29/205 ,  H01L23/482

Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

公开(公告)号：US20190096877A1

公开(公告)日：2019-03-28

申请号：US16081012

申请日：2016-04-08

Applicant: Power Integrations, Inc.

Inventor： Alexey Kudymov ,  Jamal Ramdani

IPC: H01L27/06 ,  H01L29/165 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/8605 ,  H01L21/8252

Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.

公开(公告)号：US10170438B2

公开(公告)日：2019-01-01

申请号：US15592930

申请日：2017-05-11

Applicant: Power Integrations, Inc.

Inventor： Alexey Kudymov ,  Jamal Ramdani

IPC: H01L27/088 ,  H01L23/60 ,  H03K17/081 ,  H01L29/40 ,  H01L29/778 ,  H01L29/20 ,  H01L27/06 ,  H01L27/02 ,  H01L29/205 ,  H01L29/66 ,  H01L21/8252

Abstract: A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential. The charge distribution structure is capacitively coupled to a first terminal of the semiconductor device. The static discharge system removes charge that accumulates on at least a subset of the conductors. The static discharge system removes the charge that accumulates on the subset of conductors when the semiconductor device is in a first state while allowing charge to accumulate on the subset of conductors when the semiconductor device is in a second state.

公开(公告)号：US09722063B1

公开(公告)日：2017-08-01

申请号：US15096132

申请日：2016-04-11

Applicant: POWER INTEGRATIONS, INC.

Inventor： Alexey Kudymov ,  Linlin Liu ,  Xiaohui Wang ,  Jamal Ramdani

IPC: H01L23/00 ,  H01L21/00 ,  H01L29/00 ,  H01L29/778 ,  H01L23/31 ,  H01L29/40 ,  H01L29/417 ,  H01L23/29 ,  H01L29/51 ,  H01L21/02 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L21/0217 ,  H01L21/32136 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7786

Abstract: A high-voltage field effect transistor (HFET) includes a first semiconductor material, a second semiconductor material, and a heterojunction. The heterojunction is disposed between the first semiconductor material and the second semiconductor material. The HFET also includes a plurality of composite passivation layers, where a first composite passivation layer includes a first insulation layer and a first passivation layer, and a second composite passivation layer includes a second insulation layer and a second passivation layer. A gate dielectric is disposed between the first passivation layer and the second semiconductor material. A gate electrode is disposed between the gate dielectric and the first passivation layer. A first gate field plate is disposed between the first passivation layer and the second passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a source field plate is coupled to the source electrode.

公开(公告)号：US09306014B1

公开(公告)日：2016-04-05

申请号：US14581645

申请日：2014-12-23

Applicant: POWER INTEGRATIONS, INC.

Inventor： Alexey Kudymov ,  Jamal Ramdani ,  Linlin Liu

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/404 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786

Abstract: High-electron-mobility transistors that include field plates are described. In a first implementation, a HEMT includes a first and a second semiconductor material disposed to form a heterojunction at which a two-dimensional electron gas arises and source, a drain, and gate electrodes. The gate electrode is disposed to regulate conduction in the heterojunction between the source electrode and the drain electrode. The gate has a drain-side edge. A gate-connected field plate is disposed above a drain-side edge of the gate electrode and extends laterally toward the drain. A second field plate is disposed above a drain-side edge of the gate-connected field plate and extends laterally toward the drain.

Abstract translation: 描述了包括场板的高电子迁移率晶体管。 在第一实施方案中，HEMT包括第一和第二半导体材料，其设置成形成二维电子气产生的异质结，源极，漏极和栅电极。 栅电极设置成调节源电极和漏电极之间的异质结中的导通。 门具有排水侧边缘。 栅极连接的场板设置在栅电极的漏极侧边缘的上方并且横向地朝向漏极延伸。 第二场板设置在栅极连接的场板的漏极侧边缘的上方，并且朝向漏极横向延伸。

公开(公告)号：US11373873B2

公开(公告)日：2022-06-28

申请号：US16857049

申请日：2020-04-23

Applicant: Power Integrations, Inc.

Inventor： Alexey Kudymov ,  LinLin Liu ,  Jamal Ramdani

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L23/482 ,  H01L21/285

Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

公开(公告)号：US20220013660A1

公开(公告)日：2022-01-13

申请号：US17362917

申请日：2021-06-29

Applicant: Power Integrations, Inc.

Inventor： Alexey Kudymov ,  Linlin Liu ,  Xiaohui Wang ,  Jamal Ramdani

IPC: H01L29/778 ,  H01L29/205 ,  H01L23/31 ,  H01L29/40 ,  H01L23/29 ,  H01L29/417 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/20 ,  H01L21/02 ,  H01L29/51

Abstract: An HFET includes a first and second semiconductor material. A first composite passivation layer includes a first insulation layer and a first passivation layer, and the first passivation layer is disposed between the first insulation layer and the second semiconductor material. The HFET includes a second passivation layer, where the first insulation layer is disposed between the first passivation layer and the second passivation layer. A gate dielectric is disposed between the second semiconductor material and the first passivation layer. A source electrode and a drain electrode are coupled to the second semiconductor material, and a gate electrode is disposed laterally between the source electrode and the drain electrode. A first gate field plate is disposed between the first passivation layer and the second passivation layer and electrically connected to the gate electrode, and a second gate field plate is disposed above first gate field plate.

公开(公告)号：US10204791B1

公开(公告)日：2019-02-12

申请号：US15713457

申请日：2017-09-22

Applicant: Power Integrations, Inc.

Inventor： Alexey Kudymov ,  LinLin Liu ,  Jamal Ramdani

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/20 ,  H01L23/498 ,  H01L21/285 ,  H01L29/417 ,  H01L29/778 ,  H01L29/205 ,  H01L21/00 ,  H01L21/311 ,  H01L21/768

Abstract: A high-voltage field effect transistor (HFET) includes a first active layer, a second active layer, and a layer of electrical charge disposed proximate to the first active layer and the second active layer. A gate dielectric is disposed proximate to the second active layer. A contact region in the HFET includes a contact coupled to supply or withdraw charge from the HFET, and a passivation layer disposed proximate to the contact and the gate dielectric. An interconnect extends through the passivation layer and is coupled to the contact. An interlayer dielectric is disposed proximate to the interconnect, and a plug extends into the interlayer dielectric and is coupled to the first portion of the interconnect.

公开(公告)号：US10192981B2

公开(公告)日：2019-01-29

申请号：US15448724

申请日：2017-03-03

Applicant: Power Integrations, Inc.

Inventor： Alexey Kudymov ,  Jamal Ramdani

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/20

Abstract: A semiconductor device includes a substrate and a first active layer disposed over the substrate. The semiconductor device also includes a second active layer disposed on the first active layer such that a lateral conductive channel arises between the first active layer and the second active layer. a source, gate and drain contact are disposed over the second active layer. A conductive charge distribution structure is disposed over the second active layer between the gate and drain contacts. The conductive charge distribution structure is capacitively coupled to the gate contact.

公开(公告)号：US20170179273A1

公开(公告)日：2017-06-22

申请号：US15448724

申请日：2017-03-03

Applicant: Power Integrations, Inc.

Inventor： Alexey Kudymov ,  Jamal Ramdani

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7787 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a substrate and a first active layer disposed over the substrate. The semiconductor device also includes a second active layer disposed on the first active layer such that a lateral conductive channel arises between the first active layer and the second active layer a source, gate and drain contact are disposed over the second active layer. A conductive charge distribution structure is disposed over the second active layer between the gate and drain contacts. The conductive charge distribution structure is capacitively coupled to the gate contact.