公开(公告)号：US08050645B1

公开(公告)日：2011-11-01

申请号：US12156984

申请日：2008-06-06

Applicant: Pierte Roo

Inventor： Pierte Roo

IPC: H04B1/10 ,  H04B3/20 ,  H04B1/38

CPC classification number: H04B1/581 ,  H04B3/23 ,  H04B3/32

Abstract: A communication system includes a first transmission channel with a first end and a second end. The first and second ends are coupled to first and second transformers. First and second end transceivers transmit and receive signals via the first and second transformers. A first signal is supplied at the first end and comprises a transmission signal component of the first transceiver and a receive signal component from the second transceiver. The communication system comprises a replica transmitter that generates a replica of the transmission signal component of the first transceiver. A filter filters the replica signal. An active resistive summer receives the first signal and the filtered replica signal as inputs to reduce the transmission signal component at an output of the active resistive summer. The active resistive summer includes a feedback element.

Abstract translation: 通信系统包括具有第一端和第二端的第一传输信道。 第一和第二端耦合到第一和第二变压器。 第一和第二端收发器经由第一和第二变压器发送和接收信号。 在第一端提供第一信号，并且包括第一收发器的发送信号分量和来自第二收发器的接收信号分量。 通信系统包括生成第一收发器的发送信号分量的副本的副本发送器。 A滤波器对复制信号进行滤波。 有源电阻加法器接收第一信号和滤波后的复制信号作为输入，以减少有源电阻夏季输出端的传输信号分量。 有源电阻夏季包括反馈元件。

公开(公告)号：US08009073B2

公开(公告)日：2011-08-30

申请号：US12689066

申请日：2010-01-18

Applicant: Sehat Sutardja ,  Pierte Roo

Inventor： Sehat Sutardja ,  Pierte Roo

IPC: H03M1/66

CPC classification number: H04L25/0272 ,  H03M1/661 ,  H03M1/742 ,  H04L25/03834

Abstract: A circuit configured to generate an analog signal having a pre-determined pattern. The circuit includes a plurality of digital-to-analog converters. Each of the plurality of digital-to-analog converters includes a plurality of current sources configured to generate a plurality of square waveforms and a summer configured to sum the plurality of square waveforms to generate the analog signal having the pre-determined pattern. Each square waveform is delayed by a pre-determined amount delay relative to another square waveform of the plurality of square waveforms. The pre-determined amount of delay between each square waveform of the plurality of waveforms is adjustable to adjust the pre-determined pattern of the analog signal. The pre-determined amount of delay is non-uniform throughout the circuit.

Abstract translation: 一种被配置为产生具有预定模式的模拟信号的电路。 电路包括多个数模转换器。 多个数模转换器中的每一个包括被配置为产生多个方波的多个电流源和加法器，其被配置为对多个方波进行求和以产生具有预定模式的模拟信号。 相对于多个平方波形中的另一方波形，每个方波被延迟预定量的延迟。 多个波形的每个方波之间的预定量的延迟是可调节的，以调整模拟信号的预定模式。 在整个电路中，预定量的延迟是不均匀的。

公开(公告)号：US07949078B1

公开(公告)日：2011-05-24

申请号：US12621703

申请日：2009-11-19

Applicant: Jafar Savoj ,  Pierte Roo

Inventor： Jafar Savoj ,  Pierte Roo

IPC: H04L27/06

CPC classification number: H04L27/0006 ,  H04W52/0232

Abstract: In a high-precision signal detection apparatus and method for a high-speed receiver, signal detection occurs asynchronously of the incoming data. A comparison clock is generated by an oscillator whose effective capacitance is varied by a second, lower speed oscillator connected to the capacitance. This prevents the asynchronous sampling that occurs in a zero-crossing position in the incoming data from remaining in that position in subsequent sampling cycles, so that a valid signal is not missed by the detector.

Abstract translation: 在用于高速接收机的高精度信号检测装置和方法中，信号检测与输入数据异步发生。 比较时钟由有效电容由连接到电容的第二低速振荡器变化的振荡器产生。 这样可防止在后续采样周期中输入数据中的过零位置中发生的异步采样保持在该位置，从而不会被检测器遗漏有效信号。

公开(公告)号：US07903777B1

公开(公告)日：2011-03-08

申请号：US10790689

申请日：2004-03-03

Applicant: Pierte Roo

Inventor： Pierte Roo

IPC: H03D3/24

CPC classification number: H04L7/0033 ,  H03D3/248 ,  H04L7/0337

Abstract: A system for reducing electromagnetic interference and ground bounce in an information communication system includes a plurality of information communication devices. Each of the plurality of information communication devices is responsive to a respective information communication clock signal. Each information communication clock signal of each of the plurality of information communication devices is associated with a common reference clock signal. The system includes a phase controller. The phase controller is responsive to the common reference clock signal. The phase controller alters a phase of each information communication clock signal of each of the plurality of information communication devices by a predetermined amount.

Abstract translation: 用于减少信息通信系统中的电磁干扰和地面反弹的系统包括多个信息通信装置。 多个信息通信装置中的每一个响应各自的信息通信时钟信号。 多个信息通信设备中的每一个的每个信息通信时钟信号与公共参考时钟信号相关联。 该系统包括一个相位控制器。 相位控制器响应公共参考时钟信号。 相位控制器将多个信息通信设备中的每一个的每个信息通信时钟信号的相位改变预定量。

公开(公告)号：US07889752B2

公开(公告)日：2011-02-15

申请号：US11857238

申请日：2007-09-18

Applicant: Sehat Sutardja ,  Pierte Roo

Inventor： Sehat Sutardja ,  Pierte Roo

IPC: H04L12/56

CPC classification number: H03K17/005 ,  H03K17/693

Abstract: A switching physical layer (PHY) device comprises a first termination network, a switching transmitter, and a switching receiver. The first termination network communicates with a first network connector. The switching transmitter includes first and second outputs, which communicate with the first termination network and a second termination network, respectively. The switching transmitter selectively outputs a transmit signal to a selected one of the first and second termination networks based on a control signal. The switching receiver includes first and second inputs, which communicate with the first and second termination networks, respectively. The switching receiver receives a receive signal from the selected one of the first and second termination networks.

Abstract translation: 交换物理层（PHY）设备包括第一终端网络，交换发射机和切换接收机。 第一终端网络与第一网络连接器通信。 切换发射机包括分别与第一终端网络和第二终端网络通信的第一和第二输出。 开关发射器基于控制信号选择性地向第一和第二终端网络中的一个输出发射信号。 切换接收机包括分别与第一和第二终端网络通信的第一和第二输入。 切换接收器从所选择的第一和第二终端网络接收接收信号。

公开(公告)号：USRE41831E1

公开(公告)日：2010-10-19

申请号：US11284395

申请日：2005-11-21

Applicant: Sehat Sutardja ,  Pierte Roo

Inventor： Sehat Sutardja ,  Pierte Roo

IPC: H03M1/66

CPC classification number: H03K5/01 ,  H03M1/0881 ,  H03M1/68 ,  H03M1/742

Abstract: A communication circuit, Ethernet controller card, and method comprises K digital-to-analog converters each receiving a corresponding digital control signal and each providing a corresponding analog control signal, wherein K is at least two; K voltage-to-current converters each providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals; and wherein the corresponding bi-level transmit signal components of each of the K voltage-to-current converters are combined to produce a J-level transmit signal, wherein J=K+1.

Abstract translation: 通信电路，以太网控制器卡和方法包括K个数模转换器，每个转换器接收相应的数字控制信号，并且每个提供相应的模拟控制信号，其中K至少为2; K个电压 - 电流转换器，每个转换器根据相应的模拟控制信号中的相应一个提供相应的双电平发射信号分量; 并且其中K个电压 - 电流转换器中的每一个的相应双电平发射信号分量被组合以产生J电平发射信号，其中J = K + 1。

公开(公告)号：US07606547B1

公开(公告)日：2009-10-20

申请号：US09920240

申请日：2001-08-01

Applicant: Pierte Roo ,  Sehat Sutardja

Inventor： Pierte Roo ,  Sehat Sutardja

IPC: H04B1/10 ,  H04B3/20 ,  H04B1/38

CPC classification number: H04L1/0041 ,  H04B1/581 ,  H04B3/23 ,  H04B3/32

Abstract: An electrical circuit in a communications channel includes a first sub-circuit having a first input which receives a composite signal that includes a transmission signal component and a receive signal component, a second input which receives a replica transmission signal, a third input which receives an analog baseline correction current, and an output which provides a receive signal which comprises the composite signal minus the replica signal. A second sub-circuit for controls the analog baseline correction current, so that the magnitude of the composite signal does not exceed a predetermined value of an operating parameter of the electrical circuit. The composite signal, the replica transmission signal, and the analog baseline correction current are directly connected together at a common node of the first sub-circuit.

Abstract translation: 通信信道中的电路包括具有第一输入的第一子电路，该第一输入端接收包括发送信号分量和接收信号分量的复合信号，接收复制发送信号的第二输入端，接收复制信号的第三输入端 模拟基线校正电流，以及提供包括复合信号减去副本信号的接收信号的输出。 用于控制模拟基准线校正电流的第二子电路，使得复合信号的幅度不超过电路的工作参数的预定值。 复合信号，复制传输信号和模拟基线校正电流在第一子电路的公共节点处直接连接在一起。

公开(公告)号：US06900686B1

公开(公告)日：2005-05-31

申请号：US10455668

申请日：2003-06-05

Applicant: Pierte Roo

Inventor： Pierte Roo

IPC: H03K17/693 ,  H03K17/62

CPC classification number: H03K17/693

Abstract: An analog switching circuit selects one of a first pair of differential outputs of a first circuit having a first common mode voltage and a second pair of differential outputs of a second circuit having a second common mode voltage. The analog switching circuit includes first and second switches having one of a source and drain that communicate with the first pair of differential outputs. Third and fourth switches have one of a source and drain that communicate with the second pair of differential outputs. An operational amplifier has a first input that communicates with the other of the source and drain of the first and third switches and a second input that communicates with the other of the source and drain of the second and fourth switches. A common mode feedback circuit communicates with the first and second inputs of the operational amplifier and maintains a common mode voltage input of the amplifier below the first and second common mode voltages.

Abstract translation: 模拟开关电路选择具有第一共模电压的第一电路的第一对差分输出和具有第二共模电压的第二电路的第二对差分输出之一。 模拟开关电路包括具有与第一对差分输出通信的源极和漏极之一的第一和第二开关。 第三和第四开关具有与第二对差分输出通信的源极和漏极之一。 运算放大器具有与第一和第三开关的源极和漏极中的另一个通信的第一输入端以及与第二和第四开关的源极和漏极中的另一个连通的第二输入端。 共模反馈电路与运算放大器的第一和第二输入进行通信，并将放大器的共模电压输入保持在第一和第二共模电压之下。

公开(公告)号：US06577114B1

公开(公告)日：2003-06-10

申请号：US09629095

申请日：2000-07-31

Applicant: Pierte Roo

Inventor： Pierte Roo

IPC: G01R2302

CPC classification number: H03H11/1291 ,  H03J2200/10

Abstract: An apparatus is provided to calibrate a target electrical circuit. The target electrical circuit includes at least a first variable capacitor and a first resistive element. The apparatus includes a second variable capacitor proportionally matched to the first variable capacitor. The apparatus also includes a measurement branch having at least a second resistive element proportionally matched to the first resistive element, and a current generator to generate a current proportionally matched to a predicted current of the target circuit. The apparatus also includes a digital loop to generate a digital code based on at least a comparison between d first voltage signal of the measurement branch and a predetermined voltage.

Abstract translation: 提供了一种用于校准目标电路的装置。 目标电路至少包括第一可变电容器和第一电阻元件。 该装置包括与第一可变电容器成比例地匹配的第二可变电容器。 该装置还包括具有与第一电阻元件成比例地匹配的至少第二电阻元件的测量分支，以及电流发生器，用于产生与目标电路的预测电流成比例地匹配的电流。 该装置还包括数字环路，用于至少基于测量分支的d个第一电压信号与预定电压之间的比较来生成数字码。

公开(公告)号：US08742790B1

公开(公告)日：2014-06-03

申请号：US13595496

申请日：2012-08-27

Applicant: Pierte Roo ,  Talip Ucar

Inventor： Pierte Roo ,  Talip Ucar

IPC: H03K19/00

CPC classification number: H03K3/356121

Abstract: A level shift circuit includes a first latch circuit configured to receive a clock signal, a digital data signal, a first supply voltage, and a second supply voltage, and generate a first output signal based on the digital data signal. The first output signal has a first voltage level corresponding to the first supply voltage, and a second voltage level corresponding to the second supply voltage. At least one capacitor is configured to receive the first output signal, and retain a voltage value corresponding to the output signal. A second latch circuit is configured to receive the voltage value, a third supply voltage, and a fourth supply voltage, and generate a second output signal based on the voltage value. The second output signal has a third voltage level corresponding to the third supply voltage and a fourth voltage level corresponding to the fourth supply voltage.

Abstract translation: 电平移位电路包括被配置为接收时钟信号，数字数据信号，第一电源电压和第二电源电压的第一锁存电路，并且基于数字数据信号产生第一输出信号。 第一输出信号具有对应于第一电源电压的第一电压电平和对应于第二电源电压的第二电压电平。 至少一个电容器被配置为接收第一输出信号，并且保持对应于输出信号的电压值。 第二锁存电路被配置为接收电压值，第三电源电压和第四电源电压，并且基于该电压值生成第二输出信号。 第二输出信号具有对应于第三电源电压的第三电压电平和对应于第四电源电压的第四电压电平。