METHODS AND SYSTEMS FOR RUNNING SECURE PIPELINE TASKS AND INSECURE PIPELINE TASKS IN THE SAME HARDWARE ENTITIES

    公开(公告)号:US20240354447A1

    公开(公告)日:2024-10-24

    申请号:US18136157

    申请日:2023-04-18

    CPC classification number: G06F21/74 G06F21/54 G06F21/556

    Abstract: A system includes a hardware entity that can perform tasks in a secure mode or in an insecure mode. The system's secure resources include a secure memory and a secure logical interface (LIF). The system's insecure resources include an insecure memory and a first insecure LIF. A security mode circuit in the hardware entity can set the hardware entity to secure mode or to insecure mode. Tasks submitted via the secure LIF are performed in secure mode. Tasks submitted via the insecure LIF are performed in insecure mode. The tasks are associated with security mode status indicators that are written to the hardware entities security mode indicator to thereby set the hardware entity into secure mode or insecure mode. The hardware entity cannot access secure resources while in insecure mode.

    Methods and systems for layer 7 hardware assist and CPU task offloads

    公开(公告)号:US11595502B2

    公开(公告)日:2023-02-28

    申请号:US17071975

    申请日:2020-10-15

    Abstract: Certain tasks related to processing layer 7 (L7) data streams, such as HTTP data streams, can be performed by an L7 assist circuit instead of by general-purpose CPUs. The L7 assist circuit can normalize URLs, Huffman decode, Huffman encode, and generate hashes of normalized URLs. A L7 data stream, which is reassembled from received network packets, includes an L7 header. L7 assist produces an augmented L7 header that is added to the L7 data stream. The CPUs can use the augmented L7 header, thereby speeding up processing. On the outbound path, L7 assist can remove the augmented L7 header and perform Huffman encoding such that the CPUs can perform other tasks.

    Resource fairness enforcement in shared IO interfaces

    公开(公告)号:US11593136B2

    公开(公告)日:2023-02-28

    申请号:US16691026

    申请日:2019-11-21

    Abstract: Described are platforms, systems, and methods for resource fairness enforcement. In one aspect, a programmable input output (IO) device comprises a memory unit, the memory unit having instructions stored thereon which, when executed by the programmable IO device, cause the programmable IO device to perform operations comprising: receiving an input from a logical interface (LIF); determining, by at least one meter, a metric regarding at least one resource used during a processing of the input through a programmable pipeline; and regulating additional input received from the LIF based on the metric and a threshold for the at least one resource.

    METHODS AND SYSTEMS FOR LOOSELY COUPLED PCIe SERVICE PROXY OVER AN IP NETWORK

    公开(公告)号:US20220374379A1

    公开(公告)日:2022-11-24

    申请号:US17326282

    申请日:2021-05-20

    Abstract: PCIe devices installed in host computers communicating with service nodes can provide virtualized and high availability PCIe functions to host computer workloads. The PCIe device can receive a PCIe TLP encapsulated in a PCIe DLLP via a PCIe bus. The TLP includes a TLP address value, a TLP requester identifier, and a TLP type. The PCIe device can terminate the PCIe transaction by sending a DLLP ACK message to the host computer in response to receiving the TLP. The TLP packet can be used to create a workload request capsule that includes a request type indicator, an address offset, and a workload request identifier. A workload request packet that includes the workload request capsule can be sent to a virtualized service endpoint. The service node, implementing the virtualized service endpoint, receives a workload response packet that includes the workload request identifier and a workload response payload.

    Variable-length packet header vectors

    公开(公告)号:US10944696B2

    公开(公告)日:2021-03-09

    申请号:US16279572

    申请日:2019-02-19

    Abstract: Methods and network interface modules for processing packet headers are provided. The method comprises: receiving a packet comprising a header and a payload; generating, using the header, an initial packet header vector (PHV); providing the initial PHV to a pipeline comprising a plurality of processing stages; and processing the initial PHV in the pipeline, wherein the processing comprises, for a current processing stage in the plurality of processing stages: receiving, by the current processing stage, an input PHV, wherein the input PHV (i) is the initial PHV or a modified version of the initial PHV and (ii) comprises one or more flits, and applying a feature to the input PHV to generate an output PHV, including increasing an initial length of the input PHV if the initial length is not sufficient to apply the feature.

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