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1.
公开(公告)号:US20240354447A1
公开(公告)日:2024-10-24
申请号:US18136157
申请日:2023-04-18
Applicant: Pensando Systems Inc.
Inventor: Michael Brian Galles , Francis Matus , Anton Sabev
CPC classification number: G06F21/74 , G06F21/54 , G06F21/556
Abstract: A system includes a hardware entity that can perform tasks in a secure mode or in an insecure mode. The system's secure resources include a secure memory and a secure logical interface (LIF). The system's insecure resources include an insecure memory and a first insecure LIF. A security mode circuit in the hardware entity can set the hardware entity to secure mode or to insecure mode. Tasks submitted via the secure LIF are performed in secure mode. Tasks submitted via the insecure LIF are performed in insecure mode. The tasks are associated with security mode status indicators that are written to the hardware entities security mode indicator to thereby set the hardware entity into secure mode or insecure mode. The hardware entity cannot access secure resources while in insecure mode.
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公开(公告)号:US11595502B2
公开(公告)日:2023-02-28
申请号:US17071975
申请日:2020-10-15
Applicant: Pensando Systems Inc.
Inventor: Michael Brian Galles , Hemant Vinchure
Abstract: Certain tasks related to processing layer 7 (L7) data streams, such as HTTP data streams, can be performed by an L7 assist circuit instead of by general-purpose CPUs. The L7 assist circuit can normalize URLs, Huffman decode, Huffman encode, and generate hashes of normalized URLs. A L7 data stream, which is reassembled from received network packets, includes an L7 header. L7 assist produces an augmented L7 header that is added to the L7 data stream. The CPUs can use the augmented L7 header, thereby speeding up processing. On the outbound path, L7 assist can remove the augmented L7 header and perform Huffman encoding such that the CPUs can perform other tasks.
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3.
公开(公告)号:US11374872B1
公开(公告)日:2022-06-28
申请号:US17115516
申请日:2020-12-08
Applicant: Pensando Systems Inc.
Inventor: Vishwas Danivas , Murty Subba Rama Chandra Kotha , Balakrishnan Raman , Sanjay Shanbhogue , Harinadh Nagulapalli , Michael Brian Galles , Neel Patel
IPC: H04L47/00 , H04L47/6275 , H04L47/62 , H04L67/1097
Abstract: A multitude of data transfer queues can have data transfer operations that are scheduled for a processing circuit to perform. Some of the data transfer queues may submit so many or such large data transfer operations that others receive little or no attention. The situation can be resolved in the data plane via a processing circuit that performs the data transfer operations in conjunction with priority evaluation operations that can assign the data transfer queues to different scheduler priority classes. A scheduler can schedule data transfer operations based on the scheduler priority classes of the data transfer queues.
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公开(公告)号:US11593136B2
公开(公告)日:2023-02-28
申请号:US16691026
申请日:2019-11-21
Applicant: Pensando Systems Inc.
Inventor: Michael Brian Galles
IPC: G06F9/455 , H04L47/50 , H04L47/70 , H04L49/00 , H04L43/0876 , G06F13/30 , H04L49/253
Abstract: Described are platforms, systems, and methods for resource fairness enforcement. In one aspect, a programmable input output (IO) device comprises a memory unit, the memory unit having instructions stored thereon which, when executed by the programmable IO device, cause the programmable IO device to perform operations comprising: receiving an input from a logical interface (LIF); determining, by at least one meter, a metric regarding at least one resource used during a processing of the input through a programmable pipeline; and regulating additional input received from the LIF based on the metric and a threshold for the at least one resource.
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公开(公告)号:US20220377027A1
公开(公告)日:2022-11-24
申请号:US17326284
申请日:2021-05-20
Applicant: Pensando Systems Inc.
Inventor: Silvano Gai , Michael Brian Galles , Mario Mazzola , Luca Cafiero , Krishna Doddapaneni , Sarat Kamisetty
IPC: H04L12/879 , H04L12/803 , H04L12/741 , G06F13/42
Abstract: PCIe devices installed in host computers communicating with service nodes can provide virtualized NVMe over fabric services. A workload on the host computer can submit an SQE on a NVMe SQ. The PCI device can read the SQE to obtain a command identifier, an OpCode, and a namespace identifier (NSID). The SQE can be used to produce a LTP packet that includes the opcode, the NSID, and a request identifier. The LTP packet can be sent to the service node, which may access a SAN in accordance with the opcode and NSID, and can respond to the LTP with a second LTP that includes the request identifier and a status indicator. The PCI device can use the status indicator and the request identifier to produce a CQE that is placed on a NVMe CQ associated with the SQ.
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公开(公告)号:US20220374379A1
公开(公告)日:2022-11-24
申请号:US17326282
申请日:2021-05-20
Applicant: Pensando Systems Inc.
Inventor: Michael Brian Galles , Silvano Gai , Mario Mazzola , Luca Cafiero , Francis Matus , Krishna Doddapaneni , Sarat Kamisetty
IPC: G06F13/40 , H04L12/741 , H04L12/24
Abstract: PCIe devices installed in host computers communicating with service nodes can provide virtualized and high availability PCIe functions to host computer workloads. The PCIe device can receive a PCIe TLP encapsulated in a PCIe DLLP via a PCIe bus. The TLP includes a TLP address value, a TLP requester identifier, and a TLP type. The PCIe device can terminate the PCIe transaction by sending a DLLP ACK message to the host computer in response to receiving the TLP. The TLP packet can be used to create a workload request capsule that includes a request type indicator, an address offset, and a workload request identifier. A workload request packet that includes the workload request capsule can be sent to a virtualized service endpoint. The service node, implementing the virtualized service endpoint, receives a workload response packet that includes the workload request identifier and a workload response payload.
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公开(公告)号:US11902184B2
公开(公告)日:2024-02-13
申请号:US17326284
申请日:2021-05-20
Applicant: Pensando Systems Inc.
Inventor: Silvano Gai , Michael Brian Galles , Mario Mazzola , Luca Cafiero , Krishna Doddapaneni , Sarat Kamisetty
IPC: H04L49/901 , H04L47/125 , G06F13/42 , H04L45/74
CPC classification number: H04L49/901 , G06F13/4282 , H04L45/74 , H04L47/125 , G06F2213/0026
Abstract: PCIe devices installed in host computers communicating with service nodes can provide virtualized NVMe over fabric services. A workload on the host computer can submit an SQE on a NVMe SQ. The PCI device can read the SQE to obtain a command identifier, an OpCode, and a namespace identifier (NSID). The SQE can be used to produce a LTP packet that includes the opcode, the NSID, and a request identifier. The LTP packet can be sent to the service node, which may access a SAN in accordance with the opcode and NSID, and can respond to the LTP with a second LTP that includes the request identifier and a status indicator. The PCI device can use the status indicator and the request identifier to produce a CQE that is placed on a NVMe CQ associated with the SQ.
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公开(公告)号:US11863467B2
公开(公告)日:2024-01-02
申请号:US17580367
申请日:2022-01-20
Applicant: Pensando Systems Inc.
Inventor: Michael Brian Galles , Vipin Jain
IPC: H04L49/00 , H04L69/22 , H04L47/32 , H04L41/5019 , H04L45/74 , H04L47/6295
CPC classification number: H04L49/3018 , H04L41/5019 , H04L47/32 , H04L69/22 , H04L45/74 , H04L47/6295
Abstract: A network appliance can have an input port that can receive network packets at line rate, two or more ingress queues, a line rate classification circuit that can place the network packets on the ingress queues at the line rate, a packet buffer that can store the network packets, and a sub line rate packet processing circuit that can process the network packets that are stored in the packet buffer. The line rate classification circuit can place a network packet on one of the ingress queues based on the network packet's packet contents. A buffer scheduler can select network packets for processing by a sub line rate packet processing circuit based on the priority levels of the ingress queues.
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9.
公开(公告)号:US20230231818A1
公开(公告)日:2023-07-20
申请号:US17580367
申请日:2022-01-20
Applicant: Pensando Systems Inc.
Inventor: Michael Brian Galles , Vipin Jain
IPC: H04L49/00 , H04L41/5019 , H04L47/32 , H04L69/22
CPC classification number: H04L49/3018 , H04L41/5019 , H04L47/32 , H04L69/22
Abstract: A network appliance can have an input port that can receive network packets at line rate, two or more ingress queues, a line rate classification circuit that can place the network packets on the ingress queues at the line rate, a packet buffer that can store the network packets, and a sub line rate packet processing circuit that can process the network packets that are stored in the packet buffer. The line rate classification circuit can place a network packet on one of the ingress queues based on the network packet's packet contents. A buffer scheduler can select network packets for processing by a sub line rate packet processing circuit based on the priority levels of the ingress to queues.
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公开(公告)号:US10944696B2
公开(公告)日:2021-03-09
申请号:US16279572
申请日:2019-02-19
Applicant: Pensando Systems Inc.
Inventor: Michael Brian Galles
IPC: H04L12/931 , H04L12/935 , H04L29/06 , H04L12/721 , H04L12/825 , H04L12/851 , H04L12/865
Abstract: Methods and network interface modules for processing packet headers are provided. The method comprises: receiving a packet comprising a header and a payload; generating, using the header, an initial packet header vector (PHV); providing the initial PHV to a pipeline comprising a plurality of processing stages; and processing the initial PHV in the pipeline, wherein the processing comprises, for a current processing stage in the plurality of processing stages: receiving, by the current processing stage, an input PHV, wherein the input PHV (i) is the initial PHV or a modified version of the initial PHV and (ii) comprises one or more flits, and applying a feature to the input PHV to generate an output PHV, including increasing an initial length of the input PHV if the initial length is not sufficient to apply the feature.
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