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公开(公告)号：US12119743B2
公开(公告)日：2024-10-15
申请号：US17295199
申请日：2019-12-11
Applicant: Power Integrations, Inc.
Inventor： Robert J. Mayell , Yueming Wang
CPC classification number: H02M1/4225 , H02M1/0035 , H02M1/0058 , H02M1/007 , H02M1/32 , H02M3/01 , H02M3/33571
Abstract: Apparatus and methods for controllable networks to vary inter-stage power transfer in a multi-stage power conversion system are disclosed herein. By using controllable networks (111-113) within the first power converter stage (102), intermediate power delivered to a subsequent or second power converter stage (104) can be varied so that the multi-stage power conversion system (100) may respond to a full load step while offering improved light load power conversion efficiency. A power estimation circuit (122) within the second power converter stage (104) can provide a control signal (C1-CN) to each of the controllable networks (111-113); the controllable networks (111-113), in turn, can provide network signals (SI, S2) to control the intermediate power delivered to the second power converter stage (104).
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公开(公告)号：US11824438B2
公开(公告)日：2023-11-21
申请号：US17311266
申请日：2019-11-26
Applicant: POWER INTEGRATIONS, INC.
Inventor： Robert J. Mayell , Yueming Wang , Roger Colbeck , Paul Walter DeMone , Steven Greig Porter , Robert W. Busse , Sorin S. Georgescu
CPC classification number: H02M1/38 , H02M1/0058 , H02M3/33571 , H02M1/0029 , H02M3/01
Abstract: A controller includes first and second half bridge sense circuits coupled to a half bridge node. The half bridge node is coupled between a high side switch and a low side switch coupled to an input. A rising slew detection circuit is coupled to the first half bridge sense circuit to output a first slew detection signal in response to a rising slew event at the half bridge node. A falling slew detection circuit is coupled to the second half bridge sense circuit to output a second slew detection signal in response to a falling slew event at the half bridge node. A control circuit coupled to output a high side drive signal to the high side switch and a low side drive signal to the low side switch in response to the first slew detection signal, the second slew detection signal, and a feedback signal.
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Patent Agency Ranking
公开(公告)号：US11476769B2
公开(公告)日：2022-10-18
申请号：US17364564
申请日：2021-06-30
Applicant: POWER INTEGRATIONS, INC.
Inventor： Robert J. Mayell , Yueming Wang , Roger Colbeck
Abstract: A power converter controller includes a control loop clock generator to generate a switching frequency signal responsive to a burst load threshold, a power signal, and a load signal. A switching frequency of the switching frequency signal is above a resonance range of an energy transfer element. A burst control circuit generates a burst on signal and a burst off signal in response to a feedback signal and a burst enable signal to operate the controller in a plurality of burst modes. A burst frequency of the burst on signal or the burst off signal is less than the resonance range of the energy transfer element. A request transmitter circuit generates a request signal responsive to the switching frequency signal, the burst on signal, and the burst off signal to control switching of a switching circuit.
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公开(公告)号：US20210399620A1
公开(公告)日：2021-12-23
申请号：US17295199
申请日：2019-12-11
Applicant: Power Integrations, Inc.
Inventor： Robert J. Mayell , Yueming Wang
Abstract: Apparatus and methods for controllable networks to vary inter-stage power transfer in a multi-stage power conversion system are disclosed herein. By using controllable networks (111-113) within the first power converter stage (102), intermediate power delivered to a subsequent or second power converter stage (104) can be varied so that the multi-stage power conversion system (100) may respond to a full load step while offering improved light load power conversion efficiency. A power estimation circuit (122) within the second power converter stage (104) can provide a control signal (Cl-CN) to each of the controllable networks (111-113); the controllable networks (111-113), in turn, can provide network signals (SI, S2) to control the intermediate power delivered to the second power converter stage (104).
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公开(公告)号：US20210384837A1
公开(公告)日：2021-12-09
申请号：US17364564
申请日：2021-06-30
Applicant: POWER INTEGRATIONS, INC.
Inventor： Robert J. Mayell , Yueming Wang , Roger Colbeck
Abstract: A power converter controller includes a control loop clock generator to generate a switching frequency signal responsive to a burst load threshold, a power signal, and a load signal. A switching frequency of the switching frequency signal is above a resonance range of an energy transfer element. A burst control circuit generates a burst on signal and a burst off signal in response to a feedback signal and a burst enable signal to operate the controller in a plurality of burst modes. A burst frequency of the burst on signal or the burst off signal is less than the resonance range of the energy transfer element. A request transmitter circuit generates a request signal responsive to the switching frequency signal, the burst on signal, and the burst off signal to control switching of a switching circuit.
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公开(公告)号：US10931203B2
公开(公告)日：2021-02-23
申请号：US16687400
申请日：2019-11-18
Applicant: POWER INTEGRATIONS, INC.
Inventor： Robert J. Mayell , Yueming Wang , Roger Colbeck , Hartley Fred Horwitz
Abstract: A controller configured for use in a power converter includes a multiplexer that receives a startup clock signal and a request clock signal. The multiplexer selects the startup signal or the request clock signal to generate a clock signal. A startup clock generates the startup clock signal to control a switching frequency of a primary switching circuit during a startup condition. A request clock generates the request clock signal in response to a request signal to control the switching frequency of the primary switching circuit after the startup condition. A control circuit receives the clock signal to generate a drive signal control the switching frequency of the primary switching circuit. The control circuit selects the startup clock signal during the startup condition. The control circuit receives an indication in the request signal of an end of an undervoltage condition and then selects the request clock signal after the startup condition.
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公开(公告)号：US11081966B2
公开(公告)日：2021-08-03
申请号：US16688660
申请日：2019-11-19
Applicant: POWER INTEGRATIONS, INC.
Inventor： Robert J. Mayell , Yueming Wang , Roger Colbeck
Abstract: A power converter controller includes a control loop clock generator to generate a switching frequency signal responsive to a burst load threshold, a power signal, and a load signal. A switching frequency of the switching frequency signal is above a mechanical audio resonance range of an energy transfer element and above an audible noise frequency. A burst control circuit generates a burst on signal and a burst off signal in response to a feedback signal and a burst enable signal to operate the controller in a plurality of burst modes. A burst frequency of the burst on signal or the burst off signal is less than the mechanical audio resonance range. A request transmitter circuit generates a request signal responsive to the switching frequency signal, the burst on signal, and the burst off signal to control switching of a switching circuit.
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