公开(公告)号：US11296741B2

公开(公告)日：2022-04-05

申请号：US17021384

申请日：2020-09-15

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yohei Asada ,  Tomoyasu Fujishima ,  Wataru Miyashita

IPC: H04B1/16 ,  H01Q1/32 ,  H03D7/16 ,  H04B1/10 ,  H04B1/30

Abstract: A receiving device includes: a frequency mixer that converts a frequency of a reception signal to a baseband; an envelope demodulator; an upper sideband demodulator; and a lower sideband demodulator. Each of the envelope demodulator, the upper sideband demodulator and the lower sideband demodulator demodulates an output from the frequency mixer. The receiving device further includes: a first adder that adds an output from the envelope demodulator and an inverted output obtained by inverting an output from the upper sideband demodulator; a second adder that adds the output from the envelope demodulator and an inverted output obtained by inverting an output from the lower sideband demodulator; and a third adder that adds the output from the envelope demodulator, an inverted output obtained by inverting an output from the first adder, and an inverted output obtained by inverting an output from the second adder, to output a demodulation signal.

公开(公告)号：US11190263B2

公开(公告)日：2021-11-30

申请号：US17031384

申请日：2020-09-24

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yohei Asada ,  Ryohei Shindo

IPC: H04L5/12 ,  H04L23/02 ,  H04B7/08 ,  H04B1/7105 ,  H04B1/76

Abstract: A receiving device includes an equalization processor including multiple delay equalizers. The equalization processor is configured to: obtain a first error between an output of one specific tap in the multiple delay equalizers and a predetermined reference value, and calculate a first weight with which the first error is minimized; cause a calculation result of the first weight to be reflected in all taps in the multiple delay equalizers except the specific tap, obtain a second error between outputs of all taps in the multiple delay equalizers and the predetermined reference value, and calculate a second weight with which the second error is minimized; and update coefficients of all taps in the multiple delay equalizers at the same timing using the calculation result of the first weight and a calculation result of the second weight, and calculate an output of the equalization processor.