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    Reducing CPU and bus power when running in power-save modes
    2.
    发明授权
    Reducing CPU and bus power when running in power-save modes 有权
    在省电模式下运行时，降低CPU和总线电源

    公开(公告)号：US07975161B2

    公开(公告)日：2011-07-05

    申请号：US11906473

    申请日：2007-10-02

    Applicant: Opher Kahn

    Inventor： Opher Kahn

    IPC: G06F1/06 ,  G06F1/08 ,  G06F1/04 ,  G06F1/12

    CPC classification number: G06F1/3203 ,  G06F1/324 ,  Y02D10/124 ,  Y02D10/126

    Abstract: A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more bus clock signal frequencies. In a power-save mode, the processor is able to generate one or more core clock signals at frequencies such that the lowest core clock signal frequency is lower than the predetermined multiple of the lowest of the one or more bus clock signal frequencies in performance mode. The processor is able to achieve this by generating the one or more bus clock signals so that the lowest of the bus clock signal frequencies in power-save mode is lower than the lowest of the bus clock signal frequencies in performance mode.

    Abstract translation: 处理系统包括总线和处理器，其核心被限制为具有不低于一个或多个总线时钟信号频率中最低的预定倍数的一个或多个核心时钟信号频率。 在省电模式下，处理器能够以频率生成一个或多个核心时钟信号，使得最低核心时钟信号频率低于性能模式中的一个或多个总线时钟信号频率中最低的预定倍数 。 处理器能够通过产生一个或多个总线时钟信号来实现这一点，使得省电模式中的最低总线时钟信号频率低于性能模式下总线时钟信号频率的最低值。

    Low latency buffer control system and method
    4.
    发明申请
    Low latency buffer control system and method 审中-公开
    低延迟缓冲控制系统和方法

    公开(公告)号：US20050086420A1

    公开(公告)日：2005-04-21

    申请号：US10994027

    申请日：2004-11-19

    Applicant: Jeffrey Wilcox ,  Opher Kahn ,  Alon Naveh

    Inventor： Jeffrey Wilcox ,  Opher Kahn ,  Alon Naveh

    IPC: G06F12/00 ,  G06F13/16

    CPC classification number: G06F13/1615 ,  Y02D10/14

    Abstract: A memory controller (MC) includes a buffer control circuit (BCC) to enable/disable buffers coupled to a terminated bus. The BCC can detect transactions and speculatively enable the buffers before the transaction is completely decoded. If the transaction is targeted for the terminated bus, the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed, thereby eliminating the “enable buffer” delay incurred in some conventional MCs. If the transaction is not targeted for the terminated bus, the BCC disables the buffers to save power. In MCs that queue transactions, the BCC can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded.

    Abstract translation: 存储器控制器（MC）包括缓冲器控制电路（BCC），用于启用/禁用耦合到终端总线的缓冲器。 BCC可以在交易完全解码之前检测事务并推测启用缓冲区。 如果交易针对终端总线，缓冲区将准备好在交易准备执行之前将信号驱动到终端总线上，从而消除了一些传统MC中引起的“启用缓冲”延迟。 如果交易没有针对终端总线，则BCC禁用缓冲区以节省电力。 在队列事务的MC中，BCC可以窥探队列以查找针对终止总线的事务，并在这些特定事务完全解码之前开始启用缓冲区。

    Mechanism for processing uncacheable streaming data
    8.
    发明申请
    Mechanism for processing uncacheable streaming data 审中-公开
    处理不可流水的数据流的机制

    公开(公告)号：US20060143402A1

    公开(公告)日：2006-06-29

    申请号：US11021662

    申请日：2004-12-23

    Applicant: Srinivas Chennupaty ,  Jack Doweck ,  Blaise Fanning ,  Prashant Sethi ,  Opher Kahn

    Inventor： Srinivas Chennupaty ,  Jack Doweck ,  Blaise Fanning ,  Prashant Sethi ,  Opher Kahn

    IPC: G06F13/00

    CPC classification number: G06F12/0831 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/383 ,  G06F12/0888

    Abstract: In one embodiment, a buffer is presented. The buffer comprises a type designator to designate that the buffer is a streaming read buffer, and a plurality of use designators to indicate whether data within the buffer has been used. The data within the buffer is an uncacheable memory type, such as Uncacheable Speculative Write Combining (USWC) memory. Furthermore, in some embodiments, the buffer is allocated upon execution of a streaming read buffer instruction. In other embodiments, the data within the buffer can only be used once and cannot be cached elsewhere in the processor.

    Abstract translation: 在一个实施例中，呈现缓冲器。 缓冲器包括用于指定缓冲器是流读取缓冲器的类型指示符，以及指示缓冲器内的数据是否已被使用的多个使用指示符。 缓冲区中的数据是不可缓存的存储器类型，例如不可缓存的推测写入组合（USWC）存储器。 此外，在一些实施例中，在执行流读取缓冲器指令时分配缓冲器。 在其他实施例中，缓冲器内的数据只能使用一次，并且不能被缓存在处理器的其他地方。

    Adaptive throttling of memory acceses, such as throttling RDRAM accesses in a real-time system
    9.
    发明授权
    Adaptive throttling of memory acceses, such as throttling RDRAM accesses in a real-time system 有权
    内存访问的自适应调节，例如在实时系统中限制RDRAM访问

    公开(公告)号：US06662278B1

    公开(公告)日：2003-12-09

    申请号：US09667649

    申请日：2000-09-22

    Applicant: Opher Kahn ,  Erez Birenzwig

    Inventor： Opher Kahn ,  Erez Birenzwig

    IPC: G06F1200

    CPC classification number: G06F1/3275 ,  G06F1/206 ,  G06F1/3203 ,  G06F13/161 ,  G11C7/04 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/225 ,  G11C8/00 ,  Y02D10/13 ,  Y02D10/14

    Abstract: Apparatus and methods to adaptively throttle accesses to memory employ a masking tool to specify the percentage of memory bandwidth available for access. The apparatus applies the mask and monitors the number of memory accesses during a throttle-monitoring window. If the number of memory accesses during the throttle-monitoring window exceeds or is fewer than the percentage of memory bandwidth specified by the mask, access to the memory continues until the end of the throttle-monitoring window. At the end of the throttle-monitoring window, the apparatus selects the next lower mask, which has a lower memory bandwidth allocation, applies the next lower mask, and monitors the number of memory accesses during the next throttle-monitoring window. If the number of memory accesses during the throttle-monitoring window is fewer than the percentage of memory bandwidth specified by the mask, at the end of the throttle-monitoring window, the apparatus selects the next higher mask, which has a higher memory bandwidth allocation, applies the next higher mask, and monitors the number of memory accesses during the next throttle-monitoring window. The mask itself comprises a series of ones and zeros indicating clock cycles where access to memory is allowed or disallowed. The pattern of the mask is designed to minimize the number of clock cycles in which memory is blocked. The apparatus and methods reduce the amount of time that memory is blocked in throttle mode, thus allowing real-time streams to proceed without interruption.

    Abstract translation: 用于自适应地限制对存储器的访问的装置和方法使用掩蔽工具来指定可用于访问的存储器带宽的百分比。 该装置应用掩模并监视节气门监视窗口期间的存储器访问次数。 如果节气门监控窗口中的存储器访问次数超过或小于掩码指定的存储器带宽的百分比，则对存储器的访问将持续到油门监视窗口的末尾。 在节气门监控窗口的末尾，设备选择具有较低内存带宽分配的下一个下掩码，应用下一个下掩码，并监视下一个油门监视窗口内的存储器访问次数。 如果节气门监视窗口内的存储器访问次数小于由掩码指定的存储器带宽的百分比，则在油门监视窗口结束时，设备选择具有较高存储器带宽分配的下一较高掩模 ，应用下一个更高的掩码，并监视下一个油门监控窗口内的存储器访问次数。 掩码本身包括一系列的一个和第零个，表示允许或不允许访问存储器的时钟周期。 掩模的图案被设计为最小化存储器被阻塞的时钟周期的数量。 该装置和方法减少了在节气门模式下存储器被阻塞的时间量，从而允许实时流不间断地进行。

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