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    Dielectric heterojunction device
    1.
    发明授权
    Dielectric heterojunction device 有权

    公开(公告)号：US11476340B2

    公开(公告)日：2022-10-18

    申请号：US17002253

    申请日：2020-08-25

    Applicant: Ohio State Innovation Foundation

    Inventor： Siddharth Rajan ,  Zhanbo Xia ,  Wyatt Moore

    IPC: H01L29/40 ,  H01L29/872 ,  H01L31/08 ,  H01L29/24

    Abstract: A device is provided that comprises a first layer deposited onto a second layer. The second layer comprises a lightly doped n-type or p-type semiconductor drift layer, and the first layer comprises a high-k material with a dielectric constant that is at least two times higher than the value of the second layer. A metal Schottky contact is formed on the first layer and a metal ohmic contact is formed on the second layer. Under reverse bias, the dielectric constant discontinuity leads to a very low electric field in the second layer, while the electron barrier created by the first layer stays almost flat. Under forward bias, electrons flow through the first layer, into the metal ohmic contact. For small values of conduction band offset or valence band offset between the first layer and the second layer, the device is expected to support efficient electron or hole transport.

    LOW TURN ON AND HIGH BREAKDOWN VOLTAGE LATERAL DIODE
    2.
    发明申请
    LOW TURN ON AND HIGH BREAKDOWN VOLTAGE LATERAL DIODE 有权

    公开(公告)号：US20210296510A1

    公开(公告)日：2021-09-23

    申请号：US17206570

    申请日：2021-03-19

    Applicant: Ohio State Innovation Foundation

    Inventor： Mohammad Wahidur Rahman ,  Siddharth Rajan

    IPC: H01L29/872 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40

    Abstract: A hybrid Schottky diode is described herein where the forward characteristics are determined by the metal-semiconductor junction, and the reverse characteristics and breakdown are determined by the metal/dielectric/semiconductor junction. Experimental demonstration of such hybrid Schottky diodes shows significant improvement in the breakdown performance with average breakdown field up to 2.22 MV/cm with reduced turn on of 0.47 V and enable state-of-art power switching figure of merit for GaN lateral Schottky diodes.

    Dielectric Passivation for Electronic Devices
    3.
    发明申请
    Dielectric Passivation for Electronic Devices 审中-公开

    公开(公告)号：US20200006500A1

    公开(公告)日：2020-01-02

    申请号：US16455736

    申请日：2019-06-27

    Applicant: Ohio State Innovation Foundation

    Inventor： Siddharth Rajan ,  Zhanbo Xia ,  Caiyu Wang

    IPC: H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L29/778 ,  H01L29/861 ,  H01L29/872

    Abstract: Dielectric super-junction transistors use combinations high dielectric relative permittivity materials and high-mobility materials. An associated electronic device includes a junction portion of a barrier layer adjacent a gate contact and a drain contact. A layered semiconductor device is configured with a junction dielectric permittivity that is greater than a channel dielectric permittivity in the channel layer. The junction portion has a dielectric structure that polarizes carriers within the junction portion such that excess charge on the gate is compensated by an opposite charge in the junction portion of the barrier layer proximate the gate. A sheet charge in the barrier layer is increased to form a depletion region with the channel layer that avoids a conductive parallel channel in the barrier layer to the drain contact.

    ENHANCEMENT MODE FIELD EFFECT TRANSISTOR WITH DOPED BUFFER AND DRAIN FIELD PLATE
    4.
    发明申请
    ENHANCEMENT MODE FIELD EFFECT TRANSISTOR WITH DOPED BUFFER AND DRAIN FIELD PLATE 审中-公开
    增强型场效应晶体管，带有DOPED缓冲器和漏极场板

    公开(公告)号：US20170033187A1

    公开(公告)日：2017-02-02

    申请号：US15225084

    申请日：2016-08-01

    Applicant: Ohio State Innovation Foundation

    Inventor： Siddharth Rajan ,  Sanyam Bajaj

    IPC: H01L29/205 ,  H01L29/16 ,  H01L29/20 ,  H01L27/06 ,  H01L29/868 ,  H01L29/861 ,  H01L23/528 ,  H01L29/40 ,  H01L29/778

    CPC classification number: H01L27/0629 ,  H01L23/528 ,  H01L29/0619 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/7786 ,  H01L29/8611 ,  H01L29/868

    Abstract: This disclosure relates to a novel approach towards enhancing the threshold voltage of an enhancement-mode field-effect-transistor (E-mode FET) using doped or polarization-graded buffer layers and utilizing drain-connected field plates to engineer peak fields. Enhancement-mode field effect transistors (E-mode FETs) with doped buffer layers replacing conventional undoped buffer layers could enable larger threshold voltages, owing to higher capacitance from the back. These FETs with larger threshold voltages, however, would experience large operational electric fields near the drain contact. Described herein are embodiments of an E-mode FET further comprised of doped buffer layer(s) in the structure of the HEMT to enable larger positive threshold voltages, with optional one or more drain field plates that modify the electric field profile in the channel of the device and improve device breakdown characteristics.

    Abstract translation: 本公开涉及一种使用掺杂或偏振梯度缓冲层来增强增强型场效应晶体管（E模式FET）的阈值电压并利用漏极连接的场板来设计峰值场的新颖方法。 具有掺杂缓冲层的增强型场效应晶体管（E型FET）代替传统的未掺杂缓冲层可以实现更大的阈值电压，这是由于后面的较高电容。 然而，具有较大阈值电压的这些FET将经历漏极接触附近的大的工作电场。 这里描述的是E模式FET的实施例，其还包括在HEMT的结构中的掺杂缓冲层以实现更大的正阈值电压，以及可选的一个或多个漏极场板，其修改通道中的电场分布 该器件并提高器件击穿特性。

    DIELECTRIC HETEROJUNCTION DEVICE
    6.
    发明申请
    DIELECTRIC HETEROJUNCTION DEVICE 有权

    公开(公告)号：US20210126094A1

    公开(公告)日：2021-04-29

    申请号：US17002253

    申请日：2020-08-25

    Applicant: Ohio State Innovation Foundation

    Inventor： Siddharth Rajan ,  Zhanbo Xia ,  Wyatt Moore

    IPC: H01L29/40 ,  H01L31/08 ,  H01L29/872

    Abstract: A device is provided that comprises a first layer deposited onto a second layer. The second layer comprises a lightly doped n-type or p-type semiconductor drift layer, and the first layer comprises a high-k material with a dielectric constant that is at least two times higher than the value of the second layer. A metal Schottky contact is formed on the first layer and a metal ohmic contact is formed on the second layer. Under reverse bias, the dielectric constant discontinuity leads to a very low electric field in the second layer, while the electron barrier created by the first layer stays almost flat. Under forward bias, electrons flow through the first layer, into the metal ohmic contact. For small values of conduction band offset or valence band offset between the first layer and the second layer, the device is expected to support efficient electron or hole transport.

    ETCHING METHODS AND PATTERNED SUBSTRATES MADE USING SAID METHODS
    7.
    发明申请
    ETCHING METHODS AND PATTERNED SUBSTRATES MADE USING SAID METHODS 有权

    公开(公告)号：US20250087479A1

    公开(公告)日：2025-03-13

    申请号：US18826539

    申请日：2024-09-06

    Applicant: Ohio State Innovation Foundation

    Inventor： Siddharth Rajan ,  Sheikh Ifatur Rahman ,  Ashok Dheenan ,  Nathan Wriedt

    IPC: H01L21/02 ,  H01L21/311

    Abstract: Disclosed herein are etching methods, patterned substrates made using said methods, and methods of use of said patterned substrates. For example, described herein are methods comprising: oxidizing at least a portion of a surface of a substrate comprising a group III-V compound, thereby forming an oxidized layer at said portion of the surface; and etching the oxidized layer by exposing the oxidized layer to an etchant; wherein: the group III-V compound comprises one or more group III elements (e.g., Al, Ga, In, B, Sc, Y, or a combination thereof) and a group V element (e.g., N, As, or Sb); the etchant comprises at least one of the group III elements; and the etchant removes oxides by the etchant reacting with the oxide to form a suboxide, which desorbs from the surface.

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