公开(公告)号：US10749811B2

公开(公告)日：2020-08-18

申请号：US15903557

申请日：2018-02-23

Applicant: NetSpeed Systems, Inc.

Inventor： Joseph Rowlands ,  Joji Philip ,  Sailesh Kumar ,  Nishant Rao

IPC: H04L12/801 ,  H04L12/913 ,  H04L12/933 ,  H04L12/937 ,  H04L12/865 ,  H04L12/947

Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

公开(公告)号：US10547514B2

公开(公告)日：2020-01-28

申请号：US15923519

申请日：2018-03-16

Applicant: NetSpeed Systems, Inc.

Inventor： Nishant Rao ,  Sailesh Kumar ,  Pier Giorgio Raponi

IPC: H04L12/24 ,  H04L12/933

Abstract: A system and method for automatic crossbar generation and router connections for Network-on-Chip (NoC) topology generation is disclosed. Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating topology for a given SoC by significantly improving system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, along with indicating system level routes to be taken for traffic flows using the NoC interconnect architecture. Aspects of the present disclosure further relate to determining optimal positions of ports within hosts so as to enable low latency and higher message transmission efficiency between the hosts. In yet another aspect, a computationally efficient NoC topology is generated based on allocation of routers and NoC channels so as to identify most efficient routes for various system flows between hosts.

公开(公告)号：US10355996B2

公开(公告)日：2019-07-16

申请号：US14519639

申请日：2014-10-21

Applicant: NetSpeed Systems

Inventor： Sailesh Kumar ,  Joji Philip ,  Eric Norige ,  Sundari Mitra

IPC: H04L12/26 ,  H04L12/803 ,  H04L12/933

Abstract: Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system.

公开(公告)号：US10074053B2

公开(公告)日：2018-09-11

申请号：US15387402

申请日：2016-12-21

Applicant: NetSpeed Systems

Inventor： Sailesh Kumar ,  Sandip Das ,  Poonacha Kongetira

IPC: G06F17/50 ,  G06N5/04 ,  G06F1/32 ,  G06N99/00

CPC classification number: G06N5/045 ,  G06F1/32 ,  G06N20/00 ,  H04L12/12 ,  H04L41/08 ,  H04L47/125 ,  Y02D50/20 ,  Y02D50/40

Abstract: An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.

公开(公告)号：US09864728B2

公开(公告)日：2018-01-09

申请号：US14726289

申请日：2015-05-29

Applicant: NetSpeed Systems

Inventor： Eric Norige ,  Sailesh Kumar

IPC: G06F15/17 ,  G06F15/78 ,  H04L12/933

CPC classification number: G06F15/7825 ,  H04L49/109

Abstract: Aspects of the present disclosure provide systems and methods for automatic generation of physically aware aggregation/distribution networks that enable optimized arrangement of a plurality of hardware elements, and provide positions and connectivity for one or more intermediate hardware elements. One or more intermediate hardware elements can be configured to aggregate signals/commands/messages/data from their corresponding hardware elements or from other intermediate hardware elements, and send the aggregated signals/commands/messages/data to a root hardware element that acts as a communication interface for the network. The intermediate hardware elements can also be configured to segregate/distribute signals/commands/message received from the root hardware element to a plurality of specified hardware elements and/or intermediate hardware elements.

公开(公告)号：US09830265B2

公开(公告)日：2017-11-28

申请号：US14085106

申请日：2013-11-20

Applicant: NETSPEED SYSTEMS

Inventor： Joe Rowlands ,  Sailesh Kumar

IPC: G06F12/00 ,  G06F12/084 ,  G06F9/50 ,  G06F12/0817 ,  G06F12/0811 ,  G06F12/0815

CPC classification number: G06F12/084 ,  G06F9/50 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/082 ,  G06F12/0826 ,  G06F12/0828

Abstract: The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as cache lines, by a plurality of agents/hosts. Control circuit of the present invention can further provide consolidation of one or more entries having a first format to a single entry having a second format when resources corresponding to the one or more entries are shared by the agents. First format can include an address and a pointer representing one of the agents, and the second format can include a sharing vector indicative of more than one of the agents. In another aspect, the second format can utilize, incorporate, and/or represent multiple entries that may be indicative of one or more resources based on a position in the directory.

公开(公告)号：US09825809B2

公开(公告)日：2017-11-21

申请号：US14726235

申请日：2015-05-29

Applicant: NetSpeed Systems

Inventor： Joji Philip ,  Sailesh Kumar

IPC: H04L12/24 ,  H04L12/947 ,  H04L12/741 ,  H04L12/46

CPC classification number: H04L41/0803 ,  H04L12/4641 ,  H04L45/745 ,  H04L49/109 ,  H04L49/251 ,  H04L49/252

Abstract: Aspects of the present disclosure relates to methods, computer readable mediums, and NoC architectures/systems/constructions that can automatically mark and configure some channel of a NoC as store-and-forward channels, and other channels of the NoC as cut-through channels, and can further resize the buffers/channels based on the given NoC specification and associated traffic profile. An aspect of the present disclosure relates to a method for configuring a first set of plurality of channels of a NoC as store-and-forward channels, and configuring a second set of plurality of channels of the NoC as cut-through channels based on the determination of idle cycles in a given NoC specification and associated traffic profile.

公开(公告)号：US09660942B2

公开(公告)日：2017-05-23

申请号：US14612807

申请日：2015-02-03

Applicant: NetSpeed Systems

Inventor： Sailesh Kumar

IPC: H04J3/16 ,  H04L12/861 ,  H04L12/933

CPC classification number: H04L49/9005 ,  H04L41/12 ,  H04L43/0888 ,  H04L43/0894 ,  H04L45/586 ,  H04L47/283 ,  H04L49/109

Abstract: The present disclosure relates to automatic sizing of NoC channel buffers of one or more virtual channels to optimize NoC design, SoC design, and to meet defined performance objectives. The present disclosure further relates to a NoC element such as a router or a bridge having input ports associated with input virtual channels, and output ports associated with output virtual channels, wherein, aspects of the present disclosure enable sizing of any or a combination of the width of the input virtual channel(s), width of the output virtual channel(s), buffer(s) associated with input virtual channels, and buffer(s) associated with output virtual channels. In another aspect, the sizing can be performed based on one or a combination of defined performance objectives, throughputs of the input virtual channels, and throughputs of the output virtual channels, load characteristics, bandwidth characteristics of each input/output channel, among other like parameters.

公开(公告)号：US20170060204A1

公开(公告)日：2017-03-02

申请号：US14498907

申请日：2014-09-26

Applicant: NetSpeed Systems

Inventor： Anup Gangwar ,  Vishnu Mohan Pusuluri ,  Poonacha Kongetira ,  Sailesh Kumar

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.

Abstract translation: 本公开的系统和方法涉及从具有NoC设计规范，业务规范，业务简档，功率简档信息的一个或组合的给定输入规范自动和/或动态地生成用于SoC和NoC架构的一个或多个功率管理序列 ，发起者 - 消费者关系，组件之间的相互依赖性，保留信息，外部因素以及其他联盟配置/信息，以实现一个或多个硬件元件从一个功率配置文件到另一个功率配置文件的高效切换。

公开(公告)号：US09568970B1

公开(公告)日：2017-02-14

申请号：US14620710

申请日：2015-02-12

Applicant: NetSpeed Systems

Inventor： Rimu Kaushal ,  Anup Gangwar ,  Vishnu Mohan Pusuluri ,  Sailesh Kumar

IPC: G06F1/32 ,  G06F1/28 ,  G06F1/26

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3296 ,  G06F15/7825 ,  H04L49/109 ,  H04L49/40 ,  Y02D10/171 ,  Y02D10/172

Abstract: Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a SoC/NoC that can be configured to generate and/or execute power profile management instructions using a hybrid combination of software and hardware, wherein the hardware element can be run in parallel with other hardware elements of the SoC/NoC to generate and execute power profile management instructions for different segments or regions of the SoC/NoC for efficient and safe working thereof.

Abstract translation: 本公开的方面涉及用于功率配置文件管理指令的生成和/或执行的混合和/或分布式实现的方法和系统。 本公开的实施例提供了可以被配置为使用软件和硬件的混合组合来生成和/或执行功率简档管理指令的SoC / NoC的硬件元件，其中所述硬件元件可以与其他硬件并行地运行 SoC / NoC的元素，用于生成和执行SoC / NoC的不同段或区域的功率配置文件管理指令，用于其有效和安全的工作。