公开(公告)号：US20230062352A1

公开(公告)日：2023-03-02

申请号：US17403054

申请日：2021-08-16

Applicant: NVIDIA Corporation

Inventor： Eric Masson ,  Ankur Saxena ,  Donald Bittel

IPC: H04N19/60 ,  H04N19/147

Abstract: Disclosed approaches may provide for non-blocking video processing pipelines that have the ability to efficiently share transform hardware resources. Transform hardware resources may be shared across processing parameters, such as pixel block dimensions, transform types, video stream bit depths, and/or multiple coding formats, as well as for inter-frame and intra-frame encoding. The video processing pipeline may be divided into phases, each phase having half-butterfly circuits to perform a respective portion of computations of a transform. The phases may be selectable and configurable to perform transforms for multiple different combinations of the processing parameters. In each configuration, the phases may be capable of performing a transform by a sequential pass through at least some of the phases resulting in high throughput. Approaches are also described related to improving the performance and efficiency of transpose operations of transforms.

公开(公告)号：US11647227B2

公开(公告)日：2023-05-09

申请号：US17403054

申请日：2021-08-16

Applicant: NVIDIA Corporation

Inventor： Eric Masson ,  Ankur Saxena ,  Donald Bittel

IPC: H04N19/60 ,  H04N19/147 ,  G11C7/10

CPC classification number: H04N19/60 ,  H04N19/147 ,  G11C7/1051 ,  G11C7/1078

Abstract: Disclosed approaches may provide for non-blocking video processing pipelines that have the ability to efficiently share transform hardware resources. Transform hardware resources may be shared across processing parameters, such as pixel block dimensions, transform types, video stream bit depths, and/or multiple coding formats, as well as for inter-frame and intra-frame encoding. The video processing pipeline may be divided into phases, each phase having half-butterfly circuits to perform a respective portion of computations of a transform. The phases may be selectable and configurable to perform transforms for multiple different combinations of the processing parameters. In each configuration, the phases may be capable of performing a transform by a sequential pass through at least some of the phases resulting in high throughput. Approaches are also described related to improving the performance and efficiency of transpose operations of transforms.

公开(公告)号：US11750226B2

公开(公告)日：2023-09-05

申请号：US17343136

申请日：2021-06-09

Applicant: NVIDIA CORPORATION

Inventor： Eric Masson ,  Nagaraju Balasubramanya

IPC: H03M13/29 ,  G06F11/10

CPC classification number: H03M13/2906 ,  G06F11/1076

Abstract: Various embodiments include an error correction code (ECC) system that provides protection against various errors in addition to data bit errors. In general, ECC codes protect against data bit errors, where one or more data bits in a data word contain the wrong value. The ECC code is based on the original data bits, such that a data bit error results in a data word that is inconsistent with the ECC code generated for and stored with the data word. The present embodiments generate ECC codes based on address information and/or sequencing information in addition to the data bits in the data word. As a result, the present embodiments detect bit errors in this address information and/or sequencing information. Such errors include write address decoding errors, read address decoding errors, write enable errors, and stale data errors.