公开(公告)号：US11776924B2

公开(公告)日：2023-10-03

申请号：US17546275

申请日：2021-12-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Pei-Jhen Wu ,  Ching-Hung Chang ,  Hsih-Yang Chiu

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/76895 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/039 ,  H01L2224/05547 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

公开(公告)号：US10734338B2

公开(公告)日：2020-08-04

申请号：US16268954

申请日：2019-02-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Pei-Jhen Wu ,  Chiang-Lin Shih ,  Hsih-Yang Chiu

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/522

Abstract: The present disclosure relates to a multi-ring bonding pad, a semiconductor structure having the multi-ring bonding pad, and a method of manufacturing the semiconductor structure. The bonding pad includes an inner ring member, an outer ring member, and multiple bridge members. The inner ring member has a pair of first inner edges opposite to each other, a pair of second inner edges opposite to each other, and multiple third inner edges for connecting the first inner edges to the second inner edges. The outer ring member surrounds the inner ring member and has a pair of first outer edges opposite to each other, a pair of second outer edges opposite to each other, and multiple third outer edges for connecting the first outer edges to the second outer edges. The bridge members are disposed between the inner ring member and the outer ring member for connecting the inner ring member to the outer ring member.

公开(公告)号：US11205607B2

公开(公告)日：2021-12-21

申请号：US16739106

申请日：2020-01-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Hsih-Yang Chiu ,  Ching-Hung Chang ,  Pei-Jhen Wu

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00

Abstract: A semiconductor structure and a method of manufacturing thereof are provided. The semiconductor includes a semiconductor integrated circuit device and a redistribution layer structure. The semiconductor integrated circuit device has a top surface and an electrode on the top surface. The redistribution layer structure is formed on the top surface. The redistribution layer structure includes an oxide layer, a nitride layer, a dielectric layer, a groove and a through via. The oxide layer and the nitride layer are formed on the top surface. The dielectric layer is formed on the nitride layer. The groove is formed at a topside of the dielectric layer and overlaps the electrode. The through via is formed at a bottom of the groove and extends within the electrode through the dielectric layer, the nitride layer and the oxide layer. The through via and the groove are filled with a conductive material.

公开(公告)号：US11189545B2

公开(公告)日：2021-11-30

申请号：US16447381

申请日：2019-06-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Pei-Jhen Wu

IPC: H01L23/48 ,  H01L23/00

Abstract: A semiconductor device includes a plurality of first semiconductor dies, a first adhesive layer, a plurality of second semiconductor dies, a second adhesive layer, and a plurality of first metal bumps. The first semiconductor dies are embedded in a first photosensitive layer of a first group of wafers. The first adhesive layer is disposed between at least two of the first group of wafers to form a first structure. The second semiconductor dies are embedded in a second photosensitive layer of a second group of wafers. The second adhesive layer is disposed between at least two of the second group of wafers to form a second structure. The first metal bumps are disposed between the first structure and second structure, in which the first structure is connected to the second structure with the first metal bumps.

公开(公告)号：US11699635B2

公开(公告)日：2023-07-11

申请号：US17495250

申请日：2021-10-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Pei-Jhen Wu

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L24/17 ,  H01L24/33

Abstract: A method for manufacturing a semiconductor device includes preparing a first group of wafers having a plurality of first semiconductor dies embedded in a first photosensitive material layer; forming a plurality of first through vias in the first photosensitive material layer; attaching at least two of the first group of wafers using a first adhesive layer to form a first structure; preparing a second group of wafers having a plurality of second semiconductor dies embedded in a second photosensitive material layer; forming a plurality of second through vias in the second photosensitive material layer; attaching at least two of the second group of wafers using a second adhesive layer to form a second structure; and connecting the first structure to the second structure with a plurality of first metal bumps.

公开(公告)号：US11545571B2

公开(公告)日：2023-01-03

申请号：US17230951

申请日：2021-04-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Pei-Jhen Wu ,  Hsih-Yang Chiu

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: The semiconductor device includes a first source/drain layer, a dielectric layer, a channel, a gate electrode, a first gate dielectric layer, a seed layer, a conductive layer, and a second source/drain layer. The dielectric layer is disposed on the first source/drain layer, in which the dielectric layer has a hole penetrating the dielectric layer. The channel is disposed in the hole and extends substantially perpendicular to an upper surface of the first source/drain layer. The gate electrode surrounds the channel. The first gate dielectric layer is disposed between the gate electrode and the channel. The seed layer is disposed between the gate electrode and the dielectric layer and on an upper surface of the dielectric layer, in which the seed layer covers a portion of a sidewall of the hole.

公开(公告)号：US11411006B1

公开(公告)日：2022-08-09

申请号：US17232953

申请日：2021-04-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yu-Ting Lin ,  Pei-Jhen Wu

IPC: H01L27/108

Abstract: The present disclosure provides a manufacturing method of a memory structure. The manufacturing method includes the operations of: receiving a substrate; forming a landing pad layer in the substrate; forming trenches over the landing pad layer; and forming a top pad over the trenches to form the capacitor array. The operation of forming the trenches over the landing pad layer includes the operations of: forming an integrated layer having an array pattern over the landing pad layer; forming, by a chop mask, a masking layer to mask an edge portion of the array pattern so as to define a rectangle portion of the array pattern; and etching the integrated layer according to the rectangle portion of the array pattern to form the plurality of trenches. The edge portion of the array pattern surrounds the rectangle portion of the array pattern.

公开(公告)号：US11728425B2

公开(公告)日：2023-08-15

申请号：US18060972

申请日：2022-12-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Pei-Jhen Wu ,  Hsih-Yang Chiu

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/4232 ,  H01L29/66666

Abstract: The semiconductor device includes a first source/drain layer, a dielectric layer, a channel, a gate electrode, a first gate dielectric layer, a seed layer, a conductive layer, and a second source/drain layer. The dielectric layer is disposed on the first source/drain layer, in which the dielectric layer has a hole penetrating the dielectric layer. The channel is disposed in the hole and extends substantially perpendicular to an upper surface of the first source/drain layer. The gate electrode surrounds the channel. The first gate dielectric layer is disposed between the gate electrode and the channel. The seed layer is disposed between the gate electrode and the dielectric layer and on an upper surface of the dielectric layer, in which the seed layer covers a portion of a sidewall of the hole.

公开(公告)号：US11270962B2

公开(公告)日：2022-03-08

申请号：US16665408

申请日：2019-10-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Pei-Jhen Wu ,  Ching-Hung Chang ,  Hsih-Yang Chiu

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor component, a re-routing layer, a bonding dielectric and an insulating layer. The re-routing layer is disposed over the semiconductor component and electrically coupled to the semiconductor component. The bonding dielectric is disposed over the semiconductor component to surround a top portion of the re-routing layer. The insulating layer is disposed between the semiconductor component and the bonding dielectric to surround a bottom portion of the re-routing layer.

公开(公告)号：US11217560B2

公开(公告)日：2022-01-04

申请号：US16665310

申请日：2019-10-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Pei-Jhen Wu ,  Ching-Hung Chang ,  Hsih-Yang Chiu

IPC: H01L25/065 ,  H01L23/00

Abstract: The present disclosure provides a die assembly. The die assembly includes a first die, a second die and a third die stacked together. The first die includes a plurality of first metal lines facing a plurality of second metal lines of the second die, and a second substrate beneath the second metal lines faces a plurality of third metal lines of the third die. The die assembly further includes at least one first plug, a first redistribution layer and a second redistribution layer. The first plug penetrates through the second substrate to connect to at least one of the second metal lines. A first redistribution layer physically connects at least one of the first metal lines to at least one of the second metal lines, and a second redistribution layer physically connects at least one of the third metal lines to the first plug.