公开(公告)号：US11143690B2

公开(公告)日：2021-10-12

申请号：US16591607

申请日：2019-10-02

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsueh-Han Lu ,  Jui-Hsiu Jao

IPC: G01R31/26 ,  G01R27/26 ,  H01L23/522

Abstract: A testing structure is disclosed. The testing structure includes a first layer, a second layer, and a third layer. The first layer includes a first pattern. The third layer includes a second pattern. The first layer, the second layer, and the third layer overlap each other. The second layer is connected to a CBCM (charged based capacitance measurement) testing circuit.

公开(公告)号：US11569228B2

公开(公告)日：2023-01-31

申请号：US17336292

申请日：2021-06-01

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Hsueh-Han Lu ,  Yu-Ting Lin ,  Tsang-Po Yang

IPC: H01L27/088 ,  G01R31/26 ,  H01L27/108 ,  H01L29/78

Abstract: A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.

公开(公告)号：US11410893B1

公开(公告)日：2022-08-09

申请号：US17163551

申请日：2021-01-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yu-Che Li ,  Tsang-Po Yang ,  Hsueh-Han Lu

IPC: H01L21/66 ,  H01L29/36 ,  H01L29/08

Abstract: The semiconductor structure includes a substrate, a deep well, a first doped region, a source/drain region, and a first heavily doped region. The substrate has a first conductivity type. The deep well has a second conductivity type disposed on the substrate. The first doped region has the first conductivity type disposed on the deep well. The source/drain region has the second conductivity type disposed on the first doped region. The first heavily doped region has the second conductivity type disposed in a first top region of the source/drain region, in which the first conductivity type is opposite to the second conductivity type.

公开(公告)号：US12198991B2

公开(公告)日：2025-01-14

申请号：US17661751

申请日：2022-05-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Hsueh-Han Lu ,  Yu-Ting Lin

IPC: H10B12/00 ,  H01L21/66

Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate and the bit line structure. A first landing pad is disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and electrically connects the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad, in which a first upper surface of the first landing pad is entirely covered by the conductive layer, and the conductive layer has a substantially planar upper surface.

公开(公告)号：US11950408B2

公开(公告)日：2024-04-02

申请号：US17653658

申请日：2022-03-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Hsueh-Han Lu ,  Yu-Ting Lin

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/09 ,  H10B12/34 ,  H10B12/50

Abstract: A method of manufacturing a semiconductor structure is provided. A conductive layer is formed on a precursor memory structure. A target layer is formed on the conductive layer. A first photoresist with a first opening is formed on the target layer. A spacer is formed on sidewalls of the first opening. A second photoresist with a second opening is formed on the target layer and the spacer. The target layer is patterned by the second photoresist and the spacer to form a first patterned target layer. A third photoresist with a third opening is formed on the first patterned target layer. The first patterned target layer is patterned by the third photoresist to form a second patterned target layer. The conductive layer is patterned by the second patterned target layer to form a patterned conductive layer including a ring structure aligned with a source/drain region.